arm/mm/proc-feroceon.S

75 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
98 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
99 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
101 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
119 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
120 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
131 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
156 2:	mcr	p15, 0, ip, c7, c14, 2		@ clean + invalidate D set/way
164 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
165 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
185 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
186 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
188 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
189 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
195 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
228 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
229 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
233 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
250 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
255 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
256 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
270 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
271 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
292 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
294 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
295 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
299 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
306 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
308 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
331 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
335 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
348 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
362 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
366 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
380 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
429 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
440 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
466 	mcreq	p15, 0, ip, c7, c5, 0		@ invalidate I cache
467 	mcreq	p15, 0, ip, c7, c10, 4		@ drain WB
470 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
487 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
492 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
512 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
513 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
526 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
527 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
529 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4