Lines Matching +full:5 +full:d
31 * the cache line size of the I and D cache
50 mov r2, #(16 << 5)
58 sub r2, r2, #(1 << 5)
94 .align 5
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
116 .align 5
141 .align 5
156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
159 subs r1, r1, #(1 << 5) @ next set
179 .align 5
185 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
188 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
209 .align 5
228 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
241 * Ensure no D cache aliasing occurs, either with itself or
247 .align 5
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
260 .align 5
266 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
267 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
288 .align 5
292 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
294 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
295 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
302 .align 5
306 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
308 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
328 .align 5
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
338 .align 5
345 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
346 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
359 .align 5
362 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
370 .align 5
377 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
378 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
422 .align 5
429 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
453 .align 5
470 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
482 .align 5
487 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
512 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
513 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
526 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
529 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4