arm/mm/proc-arm946.S

48 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
49 	bic	r0, r0, #0x00001000		@ i-cache
50 	bic	r0, r0, #0x00000004		@ d-cache
51 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
57  * Params  : r0 = address to jump to
70 	ret	r0
79 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
89 	mov	r0, #0
90 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
138 	sub	r3, r1, r0			@ calculate total size
144 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
145 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
146 	add	r0, r0, #CACHE_DLINESIZE
147 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
148 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
149 	add	r0, r0, #CACHE_DLINESIZE
151 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
152 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
153 	add	r0, r0, #CACHE_DLINESIZE
154 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
155 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
156 	add	r0, r0, #CACHE_DLINESIZE
158 	cmp	r0, r1
193 	bic	r0, r0, #CACHE_DLINESIZE - 1
194 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
195 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
196 	add	r0, r0, #CACHE_DLINESIZE
197 	cmp	r0, r1
199 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
200 	mov	r0, #0
215 	add	r1, r0, r1
216 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
217 	add	r0, r0, #CACHE_DLINESIZE
218 	cmp	r0, r1
220 	mov	r0, #0
221 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
222 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
240 	tst	r0, #CACHE_DLINESIZE - 1
241 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
245 	bic	r0, r0, #CACHE_DLINESIZE - 1
246 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
247 	add	r0, r0, #CACHE_DLINESIZE
248 	cmp	r0, r1
250 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
265 	bic	r0, r0, #CACHE_DLINESIZE - 1
266 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
267 	add	r0, r0, #CACHE_DLINESIZE
268 	cmp	r0, r1
271 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
285 	bic	r0, r0, #CACHE_DLINESIZE - 1
288 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
290 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
292 	add	r0, r0, #CACHE_DLINESIZE
293 	cmp	r0, r1
295 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
306 	add	r1, r1, r0
325 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
326 	add	r0, r0, #CACHE_DLINESIZE
330 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
336 	mov	r0, #0
337 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
338 	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
339 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
341 	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
342 	mcr	p15, 0, r0, c6, c4, 0
343 	mcr	p15, 0, r0, c6, c5, 0
344 	mcr	p15, 0, r0, c6, c6, 0
345 	mcr	p15, 0, r0, c6, c7, 0
347 	mov	r0, #0x0000003F			@ base = 0, size = 4GB
348 	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default
350 	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
352 	pr_val	r3, r0, r7, #1
355 	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
357 	pr_val	r3, r0, r7, #1
360 	mov	r0, #0x06
361 	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
362 	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
364 	mov	r0, #0x00			@ disable whole write buffer
366 	mov	r0, #0x02			@ region 1 write bufferred
368 	mcr	p15, 0, r0, c3, c0, 0
379 	mov	r0, #0x00000031
380 	orr	r0, r0, #0x00000200
381 	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
382 	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission
384 	mrc	p15, 0, r0, c1, c0		@ get control register
385 	orr	r0, r0, #0x00001000		@ I-cache
386 	orr	r0, r0, #0x00000005		@ MPU/D-cache
388 	orr	r0, r0, #0x00004000		@ .1.. .... .... ....