Lines Matching +full:2 +full:c0
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
121 bcs 2b @ entries 63 to 0
174 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
176 bcs 2b @ entries 63 to 0
197 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
199 bcs 2b @ entries 63 to 0
220 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
222 bcs 2b @ entries 63 to 0
243 2:
245 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
247 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
250 bcs 2b @ entries 63 to 0
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
313 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
317 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
318 mcr p15, 0, r0, c2, c0, 1
324 mcr p15, 0, r0, c3, c0, 0
328 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
329 mcr p15, 0, r0, c5, c0, 1
331 mrc p15, 0, r0, c1, c0 @ get control register