arm/mm/proc-arm926.S

72 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
73 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
75 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
94 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
100 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
113 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
135 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
137 1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
141 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
142 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
163 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
164 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
166 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
167 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
170 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
171 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
173 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
174 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
180 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
212 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
213 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
217 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
233 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
238 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
239 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
259 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
261 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
264 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
268 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
284 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
289 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
304 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
306 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
311 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
341 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
346 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
365 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
368 1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
371 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
372 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
374 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
390 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
392 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
412 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
413 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
426 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
427 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
429 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4