Lines Matching +full:1 +full:c0
48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
88 1: add r4, r4, #1 @ area size *= 2
89 movs r3, r3, lsr #1
90 bne 1b @ count not zero r-shift
91 orr r0, r0, r4, lsl #1 @ the area register value
92 orr r0, r0, #1 @ set enable bit
93 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
101 1: add r4, r4, #1 @ area size *= 2
102 movs r3, r3, lsr #1
103 bne 1b @ count not zero r-shift
104 orr r0, r0, r4, lsl #1 @ the area register value
105 orr r0, r0, #1 @ set enable bit
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
113 mov r0, #0x02 @ Region 1 write bufferred
115 mcr p15, 0, r0, c3, c0
118 sub r0, r0, #1 @ r0 = 0xffff
119 mcr p15, 0, r0, c5, c0 @ all read/write access
121 mrc p15, 0, r0, c1, c0 @ get control register
133 define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1