Lines Matching +full:0 +full:x3f000000
48 mrc p15, 0, r0, c1, c0, 0
49 bic r0, r0, #0x3f000000 @ bank/f/lock/s
50 bic r0, r0, #0x0000000c @ w-buffer/cache
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mov ip, #0
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
65 bic ip, ip, #0x0000000c @ ............wc..
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mov r0, #0
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
76 mcr p15, 0, r0, c6, c3 @ disable area 3~7
77 mcr p15, 0, r0, c6, c4
78 mcr p15, 0, r0, c6, c5
79 mcr p15, 0, r0, c6, c6
80 mcr p15, 0, r0, c6, c7
82 mov r0, #0x0000003F @ base = 0, size = 4GB
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
85 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
93 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
95 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
97 cmp r3, #0
98 moveq r0, #0
106 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
108 mov r0, #0x06
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
111 mov r0, #0x00 @ disable whole write buffer
113 mov r0, #0x02 @ Region 1 write bufferred
115 mcr p15, 0, r0, c3, c0
117 mov r0, #0x10000
118 sub r0, r0, #1 @ r0 = 0xffff
119 mcr p15, 0, r0, c5, c0 @ all read/write access
121 mrc p15, 0, r0, c1, c0 @ get control register
122 bic r0, r0, #0x3F000000 @ set to standard caching mode
124 orr r0, r0, #0x0000000d @ MPU/Cache/WB
146 .long 0x41807400
147 .long 0xfffffff0
148 .long 0
149 .long 0
156 .long 0
157 .long 0