arm/mm/cache-v7.S

25 	.align	2
44 	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
46 	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
62 2:	mov	ip, r0, lsl r2		@ NumSet << SetShift
64 	mcr	p15, 0, ip, c7, c6, 2
66 	bpl	2b
69 	mrc	p15, 1, r0, c0, c0, 0	@ re-read cache geometry from CCSIDR
101 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr, r0 = clidr
104 	ands	r3, r3, #7 << 1 		@ extract LoU*2 field from clidr
107 ALT_SMP(mrc	p15, 0, r2, c0, c0, 0)		@ read main ID register
129 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
131 	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
139 	cmp	r1, #2				@ see what cache we have at this level
144 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
146 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
166 	mcr	p15, 0, r5, c7, c14, 2		@ clean & invalidate by set/way
172 	add	r10, r10, #2			@ increment cache number
180 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
305 2:
309 	blo	2b