arm/mm/cache-v7.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/cache-v7.S
16 #include <asm/hardware/cache-b15-rac.h>
18 #include "proc-macros.S"
20 .arch armv7-a
25 	.align	2
44 	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
52 	mov	r3, r3, lsl r1		@ NumWays-1 shifted into bits [31:...]
54 	moveq	r1, #1			@ r1 needs value > 0 even if only 1 way
62 2:	mov	ip, r0, lsl r2		@ NumSet << SetShift
64 	mcr	p15, 0, ip, c7, c6, 2
65 	subs	r0, r0, #1		@ Set--
66 	bpl	2b
67 	subs	r3, r3, r1		@ Way--
69 	mrc	p15, 1, r0, c0, c0, 0	@ re-read cache geometry from CCSIDR
79  *	Flush the whole I-cache.
82  *	r0 - set to 0
86 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
94  *     Flush the D-cache up to the Level of Unification Inner Shareable
96  *     Corrupted registers: r0-r6, r9-r10
104 	ands	r3, r3, #7 << 1 		@ extract LoU*2 field from clidr
121  *	Flush the whole D-cache.
123  *	Corrupted registers: r0-r6, r9-r10
125  *	- mm    - mm_struct describing address space
131 	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
139 	cmp	r1, #2				@ see what cache we have at this level
140 	blt	skip				@ skip if no cache, or just i-cache
144 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
153 	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
154 	clz	r5, r4				@ find bit position of way size increment
164 	orr	r5, r5, r4			@ factor way number into r5
166 	mcr	p15, 0, r5, c7, c14, 2		@ clean & invalidate by set/way
169 	subs	r4, r4, r6			@ decrement the way
172 	add	r10, r10, #2			@ increment cache number
180 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
191  *  working outwards from L1 cache. This is done using Set/Way based cache
198 	stmfd	sp!, {r4-r6, r9-r10, lr}
201 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
203 	ldmfd	sp!, {r4-r6, r9-r10, lr}
211  *     Invalidate the I-cache to the point of unification.
214 	stmfd	sp!, {r4-r6, r9-r10, lr}
217 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
219 	ldmfd	sp!, {r4-r6, r9-r10, lr}
228  *	- mm    - mm_struct describing address space
239  *	- start - start address (may not be aligned)
240  *	- end   - end address (exclusive, may not be aligned)
241  *	- flags	- vm_area_struct flags describing address space
244  *	- we have a VIPT cache.
257  *	- start   - virtual start address of region
258  *	- end     - virtual end address of region
261  *	- the Icache does not read data from the write buffer
276  *	- start   - virtual start address of region
277  *	- end     - virtual end address of region
280  *	- the Icache does not read data from the write buffer
305 2:
309 	blo	2b
319  * isn't mapped, fail with -EFAULT.
325 	mov	r0, #-EFAULT
336  *	- addr	- kernel address
337  *	- size	- region size
364  *	- start   - virtual start address of region
365  *	- end     - virtual end address of region
394  *	- start   - virtual start address of region
395  *	- end     - virtual end address of region
416  *	- start   - virtual start address of region
417  *	- end     - virtual end address of region
438  *	- start	- kernel virtual start address
439  *	- size	- size of region
440  *	- dir	- DMA direction
451  *	- start	- kernel virtual start address
452  *	- size	- size of region
453  *	- dir	- DMA direction