arm/mm/cache-v6.S

35  *	r0 - set to 0
39 	mov	r0, #0
43 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
44 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
45 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
46 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
52 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
65 	mov	r0, #0
67 	mcr	p15, 0, r0, c7, c14, 0		@ D cache clean+invalidate
69 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
74 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
141 	bic	r0, r0, #CACHE_LINE_SIZE - 1
143  USER(	mcr	p15, 0, r0, c7, c10, 1	)	@ clean D line
144 	add	r0, r0, #CACHE_LINE_SIZE
145 	cmp	r0, r1
148 	mov	r0, #0
150 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
152 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
157 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
162  * Fault handling for the cache operation above. If the virtual address in r0
166 	mov	r0, #-EFAULT
181 	add	r1, r0, r1
182 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
185 	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
187 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate unified line
189 	add	r0, r0, #D_CACHE_LINE_SIZE
190 	cmp	r0, r1
193 	mov	r0, #0
194 	mcr	p15, 0, r0, c7, c10, 4
210 	tst	r0, #D_CACHE_LINE_SIZE - 1
211 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
213 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D line
215 	mcrne	p15, 0, r0, c7, c11, 1		@ clean unified line
226 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line
228 	mcr	p15, 0, r0, c7, c7, 1		@ invalidate unified line
230 	add	r0, r0, #D_CACHE_LINE_SIZE
231 	cmp	r0, r1
233 	mov	r0, #0
234 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
243 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
246 	mcr	p15, 0, r0, c7, c10, 1		@ clean D line
248 	mcr	p15, 0, r0, c7, c11, 1		@ clean unified line
250 	add	r0, r0, #D_CACHE_LINE_SIZE
251 	cmp	r0, r1
253 	mov	r0, #0
254 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
263 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
266 	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
268 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate line
270 	add	r0, r0, #D_CACHE_LINE_SIZE
271 	cmp	r0, r1
273 	mov	r0, #0
274 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
285 	add	r1, r1, r0
298 	add	r1, r1, r0