Lines Matching refs:r6
67 and r6, r8, r7
69 add r6, r6, r9, lsr #1
71 add r6, r6, r9, lsr #2
73 add r6, r6, r9, lsr #3
74 add r6, r6, r6, lsr #8
75 add r6, r6, r6, lsr #4
76 and r6, r6, #15 @ r6 = no. of registers to transfer.
80 subne r7, r7, r6, lsl #2 @ Undo increment
81 addeq r7, r7, r6, lsl #2 @ Undo decrement
93 andne r6, r8, #0xf00 @ { immediate high nibble
94 orrne r6, r9, r6, lsr #4 @ combine nibbles } else
95 ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
100 subne r7, r7, r6 @ Undo incrmenet
101 addeq r7, r7, r6 @ Undo decrement
110 movs r6, r8, lsl #20 @ Get offset
116 subne r7, r7, r6, lsr #20 @ Undo increment
117 addeq r7, r7, r6, lsr #20 @ Undo decrement
127 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
136 mov r6, r6, lsl r9 @ 0: LSL #!0
144 mov r6, r6, lsr r9 @ 4: LSR #!0
146 mov r6, r6, lsr #32 @ 5: LSR #32
152 mov r6, r6, asr r9 @ 8: ASR #!0
154 mov r6, r6, asr #32 @ 9: ASR #32
160 mov r6, r6, ror r9 @ C: ROR #!0
162 mov r6, r6, rrx @ D: RRX
205 and r6, r8, #0x55 @ hweight8(r8) + R bit
207 add r6, r6, r9, lsr #1
208 and r9, r6, #0xcc
209 and r6, r6, #0x33
210 add r6, r6, r9, lsr #2
212 adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
213 and r6, r6, #15 @ number of regs to transfer
216 addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
217 subne r7, r7, r6, lsl #2 @ decrement SP if POP
224 and r6, r8, #0x55 @ hweight8(r8)
226 add r6, r6, r9, lsr #1
227 and r9, r6, #0xcc
228 and r6, r6, #0x33
229 add r6, r6, r9, lsr #2
230 add r6, r6, r6, lsr #4
233 and r6, r6, #15 @ number of regs to transfer
234 sub r7, r7, r6, lsl #2 @ always decrement