arm/mach-ux500/pm.c

20 #define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
21 #define PRCM_ARM_WFI_STANDBY_WFI0		0x08
22 #define PRCM_ARM_WFI_STANDBY_WFI1		0x10
23 #define PRCM_IOCR		(prcmu_base + 0x310)
24 #define PRCM_IOCR_IOFORCE			0x1
27 #define PRCM_A9_MASK_REQ	(prcmu_base + 0x328)
28 #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ	0x1
30 #define PRCM_A9_MASK_ACK	(prcmu_base + 0x32c)
31 #define PRCM_ARMITMSK31TO0	(prcmu_base + 0x11c)
32 #define PRCM_ARMITMSK63TO32	(prcmu_base + 0x120)
33 #define PRCM_ARMITMSK95TO64	(prcmu_base + 0x124)
34 #define PRCM_ARMITMSK127TO96	(prcmu_base + 0x128)
35 #define PRCM_POWER_STATE_VAL	(prcmu_base + 0x25C)
36 #define PRCM_ARMITVAL31TO0	(prcmu_base + 0x260)
37 #define PRCM_ARMITVAL63TO32	(prcmu_base + 0x264)
38 #define PRCM_ARMITVAL95TO64	(prcmu_base + 0x268)
39 #define PRCM_ARMITVAL127TO96	(prcmu_base + 0x26C)
49 	/* Set bit 0 register value to 1 */  in prcmu_gic_decouple()
59 	return 0;  in prcmu_gic_decouple()
67 	/* Set bit 0 register value to 0 */  in prcmu_gic_recouple()
70 	return 0;  in prcmu_gic_recouple()
92 	for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {  in prcmu_gic_pending_irq()
114 	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {  in prcmu_pending_irq()
146 	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {  in prcmu_copy_gic_settings()
152 	return 0;  in prcmu_copy_gic_settings()
159 	return 0;  in ux500_suspend_enter()
186 	dist_base = of_iomap(np, 0);  in ux500_pm_init()