arm/mach-tegra/sleep-tegra30.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192  * Puts the current CPU in wait-for-event mode on the flow controller
193  * and powergates it -- flags (in R0) indicate the request type.
196  * corrupts r0-r4, r10-r12
201 	cmp	r10, #TEGRA30
202 	bne	_no_cpu0_chk	@ It's not Tegra30
221 	cmp	r10, #TEGRA30
246 	cmp	r10, #TEGRA30
252 	cmp	r10, #TEGRA30
293 	 * CPU power-gating process, to avoid loading from SDRAM which
294 	 * are not supported once SDRAM is put into self-refresh.
296 	 * disabled before putting SDRAM into self-refresh to avoid
356  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
380 	cmp	r10, #TEGRA30
421 	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
425 	cmp	r1, #TEGRA30
462 	cmp	r10, #TEGRA30
463 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
509 	cmp	r10, #TEGRA30
529 	/* Issue a ZQ_CAL for dev0 - DDR3 */
539 	/* Issue a ZQ_CAL for dev1 - DDR3 */
548 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
558 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
575 	/* Tegra114 had dual EMC channel, now config the other one */
630 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
633 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
637 	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
648  * puts memory in self-refresh for LP0 and LP1
692 	/* store enable-state of PLLs */
707 	cmp	r1, #TEGRA30
726 	cmp	r10, #TEGRA30
759 	cmp	r10, #TEGRA30
769 	cmp	r10, #TEGRA30
794 	cmp	r10, #TEGRA30
819 	cmp	r10, #TEGRA30
820 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
827 	cmp	r10, #TEGRA30
864 	bne	emcself			@ loop until DDR in self-refresh
872 	cmp	r10, #TEGRA30
879 	/* Tegra114 had dual EMC channel, now config the other one */