Lines Matching full:r0
184 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
238 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
254 ldr r0, [r2]
285 mov r4, r0
287 mov r0, #TEGRA_FLUSH_CACHE_ALL
289 mov r0, r4
305 add r3, r3, r0
307 mov32 r0, tegra30_tear_down_core
309 sub r0, r0, r1
311 add r0, r0, r1
325 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
329 mov r0, #0 @ power mode flags (!hotplug)
331 mov r0, #1 @ never return here
370 mov32 r0, TEGRA_CLK_RESET_BASE
373 str r1, [r0, #CLK_RESET_SCLK_BURST]
374 str r1, [r0, #CLK_RESET_CCLK_BURST]
376 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
377 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
383 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
384 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
385 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
396 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
397 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
398 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
407 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
408 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
411 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
412 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
414 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
416 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
417 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
428 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
430 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
432 str r1, [r0, #CLK_RESET_PLLP_BASE]
435 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
446 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
449 str r4, [r0, #CLK_RESET_SCLK_BURST]
453 str r4, [r0, #CLK_RESET_CCLK_BURST]
463 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
464 movteq r0, #:upper16:TEGRA_EMC_BASE
466 movweq r0, #:lower16:TEGRA_EMC0_BASE
467 movteq r0, #:upper16:TEGRA_EMC0_BASE
469 movweq r0, #:lower16:TEGRA124_EMC_BASE
470 movteq r0, #:upper16:TEGRA124_EMC_BASE
474 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
476 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
478 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
481 ldr r1, [r0, #EMC_CFG_DIG_DLL]
483 str r1, [r0, #EMC_CFG_DIG_DLL]
485 emc_timing_update r1, r0
490 cmpeq r0, r1
492 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
495 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
498 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
502 ldr r1, [r0, #EMC_CFG]
504 str r1, [r0, #EMC_CFG]
507 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
510 streq r1, [r0, #EMC_NOP]
511 streq r1, [r0, #EMC_NOP]
513 emc_device_mask r1, r0
516 ldr r2, [r0, #EMC_EMC_STATUS]
523 ldr r2, [r0, #EMC_FBIO_CFG5]
531 str r2, [r0, #EMC_ZQ_CAL]
541 str r2, [r0, #EMC_ZQ_CAL]
550 str r2, [r0, #EMC_MRW]
560 str r2, [r0, #EMC_MRW]
567 str r1, [r0, #EMC_REQ_CTRL]
569 str r1, [r0, #EMC_ZCAL_INTERVAL]
571 str r1, [r0, #EMC_CFG]
573 emc_timing_update r1, r0
579 cmp r0, r1
580 movne r0, r1
585 mov32 r0, TEGRA_PMC_BASE
586 ldr r0, [r0, #PMC_SCRATCH41]
587 ret r0 @ jump to tegra_resume
671 mov r0, #(1 << 28)
672 str r0, [r5, #CLK_RESET_SCLK_BURST]
677 str r0, [r5, #CLK_RESET_CCLK_BURST]
678 mov r0, #0
679 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
680 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
683 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
684 orr r0, r0, #MSELECT_CLKM
685 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
693 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
696 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
697 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
698 store_pllm_pmc_state r0, r1, r4
701 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
702 bic r0, r0, #(1 << 12)
703 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
708 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
709 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
710 bic r0, r0, #(1 << 30)
711 str r0, [r5, #CLK_RESET_PLLP_BASE]
713 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
714 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
716 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
717 bic r0, r0, #(1 << 30)
718 str r0, [r5, #CLK_RESET_PLLA_BASE]
719 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
720 bic r0, r0, #(1 << 30)
721 str r0, [r5, #CLK_RESET_PLLC_BASE]
722 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
723 bic r0, r0, #(1 << 30)
724 str r0, [r5, #CLK_RESET_PLLX_BASE]
736 mov r0, #(1 << 24)
737 str r0, [r5, #CLK_RESET_SCLK_BURST]
753 ldr r0, [r6, r2]
754 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
755 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
756 str r0, [r6, r2]
760 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
761 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
762 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
765 str r0, [r6, r2]
767 ldr r0, [r6, r2] /* memory barrier */
807 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
809 ldr r1, [r0]
820 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
822 ldreq r0, =TEGRA_EMC0_BASE
824 ldreq r0, =TEGRA124_EMC_BASE
829 str r1, [r0, #EMC_ZCAL_INTERVAL]
830 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
831 ldr r1, [r0, #EMC_CFG]
834 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
836 emc_timing_update r1, r0
843 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
848 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
851 ldr r1, [r0, #EMC_EMC_STATUS]
856 str r1, [r0, #EMC_SELF_REF]
858 emc_device_mask r1, r0
861 ldr r2, [r0, #EMC_EMC_STATUS]
867 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
870 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
871 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
875 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
877 emc_timing_update r1, r0
883 cmp r0, r1
884 movne r0, r1