Lines Matching full:r1
209 cpu_to_csr_reg r1, r3
210 add r1, r1, r12 @ virtual CSR address for this CPU
227 str r12, [r1]
235 ldr r3, [r1] @ read CSR
236 str r3, [r1] @ clear CSR
308 mov32 r1, tegra30_iram_start
309 sub r0, r0, r1
310 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
311 add r0, r0, r1
372 mov r1, #(1 << 28)
373 str r1, [r0, #CLK_RESET_SCLK_BURST]
374 str r1, [r0, #CLK_RESET_CCLK_BURST]
375 mov r1, #0
376 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
377 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
383 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
384 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
385 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
388 ldr r1, [r7]
389 add r1, r1, #2
390 wait_until r1, r7, r3
394 pllm_pmc_enable r1, r2
396 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
397 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
398 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
405 pllm_pmc_enable r1, r2
407 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
408 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
411 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
412 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
414 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
416 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
417 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
424 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
425 cmp r1, #TEGRA30
428 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
430 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
431 bic r1, r1, #(1<<31) @ disable PllP bypass
432 str r1, [r0, #CLK_RESET_PLLP_BASE]
434 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
435 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
439 ldr r1, [r7]
440 add r1, r1, #LOCK_DELAY
441 wait_until r1, r7, r3
456 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
457 mvn r1, r1
458 bic r1, r1, #(1 << 31)
459 orr r1, r1, #(1 << 30)
460 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
473 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
474 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
475 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
476 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
477 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
478 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
481 ldr r1, [r0, #EMC_CFG_DIG_DLL]
482 orr r1, r1, #(1 << 30) @ set DLL_RESET
483 str r1, [r0, #EMC_CFG_DIG_DLL]
485 emc_timing_update r1, r0
488 movweq r1, #:lower16:TEGRA_EMC1_BASE
489 movteq r1, #:upper16:TEGRA_EMC1_BASE
490 cmpeq r0, r1
492 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
493 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
494 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
495 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
498 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
499 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
502 ldr r1, [r0, #EMC_CFG]
503 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
504 str r1, [r0, #EMC_CFG]
506 mov r1, #0
507 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
508 mov r1, #1
510 streq r1, [r0, #EMC_NOP]
511 streq r1, [r0, #EMC_NOP]
513 emc_device_mask r1, r0
517 ands r2, r2, r1
520 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
536 tst r1, #2
555 tst r1, #2
566 mov r1, #0 @ unstall all transactions
567 str r1, [r0, #EMC_REQ_CTRL]
568 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
569 str r1, [r0, #EMC_ZCAL_INTERVAL]
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
571 str r1, [r0, #EMC_CFG]
573 emc_timing_update r1, r0
578 mov32 r1, TEGRA_EMC1_BASE
579 cmp r0, r1
580 movne r0, r1
674 ldr r1, [r7]
675 add r1, r1, #2
676 wait_until r1, r7, r9
688 ldr r1, [r7]
689 add r1, r1, #2
690 wait_until r1, r7, r9
693 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
696 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
697 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
698 store_pllm_pmc_state r0, r1, r4
706 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
707 cmp r1, #TEGRA30
728 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
750 cpu_id r1
752 cpu_to_csr_reg r2, r1
764 cpu_to_halt_reg r2, r1
809 ldr r1, [r0]
810 str r1, [r8, r9] @ save the content of the addr
828 mov r1, #0
829 str r1, [r0, #EMC_ZCAL_INTERVAL]
830 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
831 ldr r1, [r0, #EMC_CFG]
832 bic r1, r1, #(1 << 28)
833 bicne r1, r1, #(1 << 29)
834 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
836 emc_timing_update r1, r0
838 ldr r1, [r7]
839 add r1, r1, #5
840 wait_until r1, r7, r2
843 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
844 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
847 mov r1, #3
848 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
851 ldr r1, [r0, #EMC_EMC_STATUS]
852 tst r1, #4
855 mov r1, #1
856 str r1, [r0, #EMC_SELF_REF]
858 emc_device_mask r1, r0
862 and r2, r2, r1
863 cmp r2, r1
867 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
869 and r1, r1, r2
870 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
871 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
873 orreq r1, r1, #7 @ set E_NO_VTTGEN
874 orrne r1, r1, #0x3f
875 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
877 emc_timing_update r1, r0
882 mov32 r1, TEGRA_EMC1_BASE
883 cmp r0, r1
884 movne r0, r1
888 ldr r1, [r4, #PMC_CTRL]
889 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
895 mov32 r1, 0x8EC00000
896 str r1, [r4, #PMC_IO_DPD_REQ]