Lines Matching +full:clock +full:- +full:skip

1 /* SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2018 Chen-Yu Tsai
6  * Chen-Yu Tsai <wens@csie.org>
18 	.arch	armv7-a
20 	 * Enable cluster-level coherency, in preparation for turning on the MMU.
22 	 * Also enable regional clock gating and L2 data latency settings for
23 	 * Cortex-A15. These settings are from the vendor kernel.
34 	/* The following is Cortex-A15 specific */
36 	/* ACTLR2: Enable CPU regional clock gates */
43 	/* Enable L2, GIC, and Timer regional clock gates */
55 	/* End of Cortex-A15 specific setup */
63 	/* Skip cci_enable_port_for_self if not first comer */
69 	first: .word sunxi_mc_smp_first_comer - .