Lines Matching full:read
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
92 * (read/write).
95 * (output, read/write).
98 * (input, read/write).
101 * (read/write).
104 * (read).
106 * Controller (UDC) Data Register (read/write).
108 * Controller (UDC) Status Register (read/write).
124 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
151 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
156 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
162 /* Service request (read) */
164 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
167 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
170 /* Service request (read) */
172 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
197 * (read/write).
200 * (read/write).
203 * (read/write).
206 * (read/write).
209 * (read/write).
212 * (read/write).
214 * Receiver/Transmitter (UART) Status Register 1 (read).
218 * (read/write).
221 * (read/write).
224 * (read/write).
227 * (read/write).
230 * (read/write).
233 * (read/write).
236 * (read/write).
238 * Receiver/Transmitter (UART) Status Register 1 (read).
242 * (read/write).
245 * (read/write).
248 * (read/write).
251 * (read/write).
254 * (read/write).
257 * (read/write).
259 * Receiver/Transmitter (UART) Status Register 1 (read).
380 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
381 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
382 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
386 /* Service request (read) */
388 /* more Service request (read) */
392 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
394 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
395 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
396 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
397 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
398 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
399 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
407 * Control Register 0 (read/write).
409 * Control Register 1 (read/write).
411 * Control Register 2 (read/write).
413 * Control Register 3 (read/write).
415 * Control Register 4 (read/write).
417 * Data Register (read/write).
419 * Status Register 0 (read/write).
421 * Status Register 1 (read/write).
499 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
500 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
501 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
504 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
508 /* Service request (read) */
510 /* more Service request (read) */
512 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
513 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
514 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
515 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
517 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
518 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
519 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
527 * controller (HSSP) Control Register 0 (read/write).
529 * controller (HSSP) Control Register 1 (read/write).
531 * controller (HSSP) Data Register (read/write).
533 * controller (HSSP) Status Register 0 (read/write).
535 * controller (HSSP) Status Register 1 (read).
537 * controller (HSSP) Control Register 2 (read/write).
569 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
570 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
571 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
574 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
578 /* Service request (read) */
580 /* more Service request (read) */
583 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
584 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
585 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
586 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
587 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
588 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
589 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
608 * Control Register 0 (read/write).
610 * Data Register 0 (audio, read/write).
612 * Data Register 1 (telecom, read/write).
614 * Data Register 2 (CODEC registers, read/write).
616 * Status Register (read/write).
618 * Control Register 1 (read/write).
693 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
694 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
699 /* or less Service request (read) */
701 /* more Service request (read) */
703 /* or less Service request (read) */
705 /* or more Service request (read) */
711 /* (read) */
713 /* (read) */
715 /* (read) */
717 /* (read) */
719 /* (read) */
720 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
721 /* (read) */
722 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
723 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
737 * Register 0 (read/write).
739 * Register 1 (read/write).
743 * Register (read/write).
745 * Register (read/write).
802 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
803 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
804 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
806 /* Service request (read) */
808 /* Service request (read) */
817 * (read/write).
819 * (read/write).
821 * (read/write).
823 * (read/write).
825 * (read/write).
827 * (read/write).
829 * (read/write).
831 * (read/write).
865 * PMCR Power Manager (PM) Control Register (read/write).
866 * PSSR Power Manager (PM) Sleep Status Register (read/write).
867 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
869 * (read/write).
871 * (read/write).
873 * Configuration Register (read/write).
875 * Sleep state Register (read/write, see GPIO pins).
876 * POSR Power Manager (PM) Oscillator Status Register (read).
1021 * (read/write).
1022 * RCSR Reset Controller (RC) Status Register (read/write).
1040 * TUCR Test Unit Control Register (read/write).
1085 * Register (read).
1087 * Register (read/write).
1093 * detect Register (read/write).
1095 * detect Register (read/write).
1097 * status Register (read/write).
1099 * Function Register (read/write).
1194 * Pending register (read).
1195 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1196 * ICLR Interrupt Controller (IC) Level Register (read/write).
1198 * (read/write).
1202 * (FIQ) Pending register (read).
1203 * ICPR Interrupt Controller (IC) Pending Register (read).
1272 * Register (read/write).
1274 * (read/write).
1276 * Register (read/write).
1278 * Direction Register (read/write).
1280 * (read).
1351 * CoNFiGuration register (read/write).
1354 * (read/write).
1357 * (read/write).
1360 * (read/write).
1434 * (read/write).
1436 * (read/write).
1466 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1468 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1473 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1478 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1480 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1504 * Configuration Register (read/write).
1570 * (read/write).
1575 * (read/write).
1576 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
1578 * read and written (cleared) in versions 2.0 (rev. = 8)
1581 * (DMA) Base Address Register channel 1 (read/write).
1583 * (DMA) Current Address Register channel 1 (read).
1585 * (DMA) Base Address Register channel 2 (read/write).
1587 * (DMA) Current Address Register channel 2 (read).
1589 * (read/write).
1592 * StrongARM SA-1100, it can be written and read in
1595 * (read/write).
1598 * StrongARM SA-1100, it can be written and read in
1601 * (read/write).
1604 * StrongARM SA-1100, it can be written and read in
1692 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */