arm/mach-s3c/s3c64xx.c

1 // SPDX-License-Identifier: GPL-2.0
11 // Common Codes for S3C64XX machines
29 #include <linux/dma-mapping.h>
31 #include <linux/irqchip/arm-vic.h>
40 #include "regs-gpio.h"
41 #include "gpio-samsung.h"
46 #include "gpio-cfg.h"
47 #include "pwm-core.h"
48 #include "regs-irqtype.h"
49 #include "s3c64xx.h"
50 #include "irq-uart-s3c64xx.h"
52 /* External clock frequency */
70 	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);  in s3c64xx_init_uarts()
153 	.name		= "s3c64xx-core",
154 	.dev_name	= "s3c64xx-core",
171 	s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;  in s3c64xx_set_timer_source()
218 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
219 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
220 			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
221 			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
222 			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
223 			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
236 #define eint_offset(irq)	((irq) - IRQ_EINT(0))
244 	mask |= (u32)data->chip_data;  in s3c_irq_eint_mask()
253 	mask &= ~((u32)data->chip_data);  in s3c_irq_eint_unmask()
259 	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);  in s3c_irq_eint_ack()
264 	/* compiler should in-line these */  in s3c_irq_eint_maskack()
271 	int offs = eint_offset(data->irq);  in s3c_irq_eint_set_type()
279 		return -EINVAL;  in s3c_irq_eint_set_type()
313 		return -1;  in s3c_irq_eint_set_type()
319 		shift = ((offs - 16) / 2) * 4;  in s3c_irq_eint_set_type()
333 		pin = S3C64XX_GPL(offs + 8 - 16);  in s3c_irq_eint_set_type()
336 		pin = S3C64XX_GPM(offs - 23);  in s3c_irq_eint_set_type()
346 	.name		= "s3c-eint",
369 	status &= (1 << (end - start + 1)) - 1;  in s3c_irq_demux_eint()
403 	/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */  in s3c64xx_init_irq_eint()
405 		return -ENODEV;  in s3c64xx_init_irq_eint()
425 		"and linux-samsung-soc@vger.kernel.org if you still use it." \