Lines Matching full:r0
19 ldr r0, =PSSR
28 str r1, [r0] @ make sure PSSR_PH/STS are clear
61 mcr p14, 0, r0, c7, c0, 0
66 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
67 bic r0, r0, #PXA3_DDR_HCAL_HCEN
68 str r0, [r1, #PXA3_DDR_HCAL]
69 1: ldr r0, [r1, #PXA3_DDR_HCAL]
70 tst r0, #PXA3_DDR_HCAL_HCEN
73 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
74 orr r0, r0, #PXA3_RCOMP_SWEVAL
75 str r0, [r1, #PXA3_RCOMP]
77 mov r0, #~0 @ Clear interrupts
78 str r0, [r1, #PXA3_DMCISR]
80 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
81 orr r0, r0, #PXA3_DMCIER_EDLP
82 str r0, [r1, #PXA3_DMCIER]
84 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
85 bic r0, r0, #PXA3_DDR_HCAL_HCRNG
86 orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
87 str r0, [r1, #PXA3_DDR_HCAL]
89 1: ldr r0, [r1, #PXA3_DMCISR]
90 tst r0, #PXA3_DMCIER_EDLP
93 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
94 orr r0, r0, #PXA3_MDCNFG_DMCEN
95 str r0, [r1, #PXA3_MDCNFG]
96 1: ldr r0, [r1, #PXA3_MDCNFG]
97 tst r0, #PXA3_MDCNFG_DMCEN
100 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
101 orr r0, r0, #2 @ HCRNG
102 str r0, [r1, #PXA3_DDR_HCAL]
104 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
105 bic r0, r0, #0x20000000
106 str r0, [r1, #PXA3_DMCIER]