arm/mach-pxa/pxa3xx.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * linux/arch/arm/mach-pxa/pxa3xx.c
5  * code specific to pxa3xx aka Monahans
9  * 2007-09-02: eric miao <eric.miao@marvell.com>
13 #include <linux/dma/pxa-dma.h>
17 #include <linux/gpio-pxa.h>
25 #include <linux/platform_data/i2c-pxa.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
36 #include "addr-map.h"
49  * NAND NFC: DFI bus arbitration subset
69  * memory controller has to be reinitialised, so we place some code
72  * We disable FIQs across the standby - otherwise, we might receive a
80 		    pm_enter_standby_end - pm_enter_standby_start);  in pxa3xx_cpu_standby()
99  * PXA3xx development kits assumes that the resuming process continues
216 	switch (d->irq) {  in pxa3xx_set_wake()
288 		return -EINVAL;  in pxa3xx_set_wake()
307 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);  in pxa_ack_ext_wakeup()
313 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_mask_ext_wakeup()
319 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_unmask_ext_wakeup()
325 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);  in pxa_set_ext_wakeup_type()
328 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);  in pxa_set_ext_wakeup_type()
375 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
409 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully  in pxa3xx_init()
416 		 * somebody disables the NAND clock (unused clock) while this  in pxa3xx_init()