Lines Matching +full:power +full:- +full:up
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
5 * Taken from pxa-regs.h by Russell King
14 #include "pxa-regs.h"
17 * Power Manager
20 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
21 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
22 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
23 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
24 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
25 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
26 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
27 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
28 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
29 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
30 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
31 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
34 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
35 #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
36 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
37 #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
38 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
39 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
92 #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
99 #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
105 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
112 #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
113 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
114 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
115 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
116 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
117 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
118 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
119 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
120 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
121 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
122 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
123 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
124 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
125 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
126 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
127 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
128 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
129 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
139 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
140 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */