Lines Matching full:udc

8 #error You cannot include both PXA25x and PXA27x UDC support
11 #define UDCCR           __REG(0x40600000) /* UDC Control Register */
20 #define UDCCR_ACN	(0x03 << 11)	/* Active UDC configuration Number */
22 #define UDCCR_AIN	(0x07 << 8)	/* Active UDC interface Number */
24 #define UDCCR_AAISN	(0x07 << 5)	/* Active UDC Alternate Interface
31 #define UDCCR_UDR	(1 << 2)	/* UDC Resume */
32 #define UDCCR_UDA	(1 << 1)	/* UDC Active */
33 #define UDCCR_UDE	(1 << 0)	/* UDC Enable */
35 #define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
36 #define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
50 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
51 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
59 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
60 #define UDCOTGICR	__REG(0x40600018) /* UDC On-The-Go interrupt control */
106 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
116 #define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
117 #define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
118 #define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
119 #define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
120 #define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
121 #define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
122 #define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
123 #define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
124 #define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
125 #define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
126 #define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
127 #define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
128 #define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
129 #define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
130 #define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
131 #define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
132 #define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
133 #define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
134 #define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
135 #define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
136 #define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
137 #define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
138 #define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */