arm/mach-omap2/sleep44xx.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <asm/hardware/cache-l2x0.h>
15 #include "omap-secure.h"
19 #include "omap4-sar-layout.h"
21 	.arch armv7-a
42  * power down sequence. Calling WFI effectively changes the CPU
43  * power domains states to the desired target power state.
46  *	0 - No context lost
47  * 	1 - CPUx L1 and logic lost: MPUSS CSWR
48  * 	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49  *	3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
50  * @return: This function never returns for CPU OFF and DORMANT power states.
51  * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
54  * It returns to the caller for CPU INACTIVE and ON power states or in case
62 	stmfd	sp!, {r4-r12, lr}
76 	stmfd   r13!, {r4-r12, r14}
79 	ldmfd   r13!, {r4-r12, r14}
98 	 * the SCU power status to DORMANT or OFF mode.
113 	stmfd   r13!, {r4-r12, r14}
116 	ldmfd   r13!, {r4-r12, r14}
136 	 * Common cache-l2x0.c functions can't be used here since it
187 	 * no low power state was attempted.
196 	 * Ensure the CPU power state is set to NORMAL in
197 	 * SCU power state so that CPU is back in coherency.
198 	 * In non-coherent mode CPU can lock-up and lead to
213 	stmfd   r13!, {r4-r12, r14}
216 	ldmfd   r13!, {r4-r12, r14}
225 	ldmfd	sp!, {r4-r12, pc}
235  * ROM code jumps to this function while waking up from CPU
243 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
246 	 * OMAP443X GP devices- SMP bit isn't accessible.
247 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
251 	cmp	r9, #0x1			@ Skip if GP device
289 	beq	skip_l2en			@ Skip if already enabled
325 	.long	ppa_por_params - .
355 	 * CPU is in idle and low power state. CPU can specualatively
357 	 * NOPs as per Cortex-A9 pipeline.
379 	.long	ppa_zero_params - .