Lines Matching refs:omap2_prm_write_mod_reg

112 	omap2_prm_write_mod_reg(vp->tranxdone_status,  in omap3_prm_vp_clear_txdone()
123 omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); in omap3_prm_vcvp_write()
193 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); in omap3xxx_prm_save_and_clear_irqen()
211 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, in omap3xxx_prm_restore_irqen()
254 omap2_prm_write_mod_reg(wkst, module, wkst_off); in omap3xxx_prm_clear_mod_irqs()
274 omap2_prm_write_mod_reg( in omap3_prm_reset_modem()
278 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_prm_reset_modem()
304 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | in omap3_prm_init_pm()
308 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | in omap3_prm_init_pm()
314 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, in omap3_prm_init_pm()
326 omap2_prm_write_mod_reg(en_uart4_mask | in omap3_prm_init_pm()
339 omap2_prm_write_mod_reg(grpsel_uart4_mask | in omap3_prm_init_pm()
353 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); in omap3_prm_init_pm()
354 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); in omap3_prm_init_pm()
355 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); in omap3_prm_init_pm()
356 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, in omap3_prm_init_pm()
361 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
362 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
363 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
364 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
365 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
366 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
367 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, in omap3_prm_init_pm()
371 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); in omap3_prm_init_pm()
484 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | in omap3xxx_prm_iva_idle()
494 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); in omap3xxx_prm_iva_idle()
500 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | in omap3xxx_prm_iva_idle()
618 omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); in omap3_pwrdm_clear_all_prev_pwrst()