1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
17 #include "prm-regbits-33xx.h"
31 /* Read-modify-write a register in PRM. Caller must lock */
32 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)  in am33xx_prm_rmw_reg_bits()  argument
37 	v &= ~mask;  in am33xx_prm_rmw_reg_bits()
45  * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
47  * @shift: register bit shift corresponding to the reset line to check
54  * -EINVAL upon parameter error.
69  * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
70  * @shift: register bit shift corresponding to the reset line to assert
76  * reset line to be asserted / deasserted in order to fully enable the
77  * IP.  These modules may have multiple hard-reset lines that reset
79  * place the submodule into reset.  Returns 0 upon success or -EINVAL
85 	u32 mask = 1 << shift;  in am33xx_prm_assert_hardreset()  local
87 	am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);  in am33xx_prm_assert_hardreset()
93  * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
95  * @shift: register bit shift corresponding to the reset line to deassert
96  * @st_shift: reset status register bit shift corresponding to the reset line
103  * reset line to be asserted / deasserted in order to fully enable the
104  * IP.  These modules may have multiple hard-reset lines that reset
106  * take the submodule out of reset and wait until the PRCM indicates
107  * that the reset has completed before returning.  Returns 0 upon success or
108  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
109  * of reset, or -EBUSY if the submodule did not exit reset promptly.
116 	u32 mask = 1 << st_shift;  in am33xx_prm_deassert_hardreset()  local
118 	/* Check the current status to avoid  de-asserting the line twice */  in am33xx_prm_deassert_hardreset()
120 		return -EEXIST;  in am33xx_prm_deassert_hardreset()
122 	/* Clear the reset status by writing 1 to the status bit */  in am33xx_prm_deassert_hardreset()
123 	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);  in am33xx_prm_deassert_hardreset()
125 	/* de-assert the reset control line */  in am33xx_prm_deassert_hardreset()
126 	mask = 1 << shift;  in am33xx_prm_deassert_hardreset()
128 	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);  in am33xx_prm_deassert_hardreset()
135 	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;  in am33xx_prm_deassert_hardreset()
142 				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_set_next_pwrst()
150 	v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_read_next_pwrst()
161 	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);  in am33xx_pwrdm_read_pwrst()
172 				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_set_lowpwrstchange()
180 				pwrdm->prcm_offs, pwrdm->pwrstst_offs);  in am33xx_pwrdm_clear_all_prev_pwrst()
188 	m = pwrdm->logicretstate_mask;  in am33xx_pwrdm_set_logic_retst()
190 		return -EINVAL;  in am33xx_pwrdm_set_logic_retst()
193 				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_set_logic_retst()
202 	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);  in am33xx_pwrdm_read_logic_pwrst()
213 	m = pwrdm->logicretstate_mask;  in am33xx_pwrdm_read_logic_retst()
215 		return -EINVAL;  in am33xx_pwrdm_read_logic_retst()
217 	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_read_logic_retst()
229 	m = pwrdm->mem_on_mask[bank];  in am33xx_pwrdm_set_mem_onst()
231 		return -EINVAL;  in am33xx_pwrdm_set_mem_onst()
234 				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_set_mem_onst()
244 	m = pwrdm->mem_ret_mask[bank];  in am33xx_pwrdm_set_mem_retst()
246 		return -EINVAL;  in am33xx_pwrdm_set_mem_retst()
249 				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_set_mem_retst()
258 	m = pwrdm->mem_pwrst_mask[bank];  in am33xx_pwrdm_read_mem_pwrst()
260 		return -EINVAL;  in am33xx_pwrdm_read_mem_pwrst()
262 	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);  in am33xx_pwrdm_read_mem_pwrst()
273 	m = pwrdm->mem_retst_mask[bank];  in am33xx_pwrdm_read_mem_retst()
275 		return -EINVAL;  in am33xx_pwrdm_read_mem_retst()
277 	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_read_mem_retst()
290 	 * via a callback and a periodic timer check -- how long do we expect  in am33xx_pwrdm_wait_transition()
295 	while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)  in am33xx_pwrdm_wait_transition()
302 		       pwrdm->name);  in am33xx_pwrdm_wait_transition()
303 		return -EAGAIN;  in am33xx_pwrdm_wait_transition()
318  * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset
320  * Immediately reboots the device through warm reset.
325 	 * Historically AM33xx performed warm reset for all requested reboot_mode.  in am33xx_prm_global_sw_reset()
328 	u32 mask = AM33XX_RST_GLOBAL_WARM_SW_MASK;  in am33xx_prm_global_sw_reset()  local
331 		mask = AM33XX_RST_GLOBAL_COLD_SW_MASK;  in am33xx_prm_global_sw_reset()
333 	am33xx_prm_rmw_reg_bits(mask,  in am33xx_prm_global_sw_reset()
334 				mask,  in am33xx_prm_global_sw_reset()
345 	pwrdm->context = am33xx_prm_read_reg(pwrdm->prcm_offs,  in am33xx_pwrdm_save_context()
346 						pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_save_context()
351 	pwrdm->context &= ~AM33XX_LOWPOWERSTATECHANGE_MASK;  in am33xx_pwrdm_save_context()
358 	st = am33xx_prm_read_reg(pwrdm->prcm_offs,  in am33xx_pwrdm_restore_context()
359 				 pwrdm->pwrstst_offs);  in am33xx_pwrdm_restore_context()
361 	am33xx_prm_write_reg(pwrdm->context, pwrdm->prcm_offs,  in am33xx_pwrdm_restore_context()
362 			     pwrdm->pwrstctrl_offs);  in am33xx_pwrdm_restore_context()
366 	ctrl = OMAP_POWERSTATEST_MASK & pwrdm->context;  in am33xx_pwrdm_restore_context()