Lines Matching +full:0 +full:x0600
24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
48 #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
49 #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
52 #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
53 #define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
54 #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
55 #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
56 #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
59 #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
60 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
61 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
64 #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
65 #define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
66 #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
67 #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
68 #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
71 #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
72 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
73 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)