Lines Matching +full:12 +full:a

14  * respect to each other. These ratio sets are for a given voltage/DPLL
15  * setting. All configurations can be described by a DPLL setting and a ratio
19  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
24  * THe format described in this file is deprecated.  Once a reasonable
34  * struct prcm_config - define clock rates on a per-OPP basis (24xx)
36  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
40  * This is deprecated.  As soon as we have a decent OPP API, we should
54 	unsigned long base_sdrc_rfr;	/* base refresh timing for a set */
218  * describe DPLL combinations to go along with a ratio.
230  * #5a	(ratio1) baseport-target, target DPLL = 266*2 = 532MHz
232 #define M5A_DPLL_MULT_12		(133 << 12)
237 #define M5A_DPLL_MULT_13		(61 << 12)
242 #define M5A_DPLL_MULT_19		(55 << 12)
248 #define M5B_DPLL_MULT_12		(50 << 12)
253 #define M5B_DPLL_MULT_13		(200 << 12)
254 #define M5B_DPLL_DIV_13			(12 << 8)
259 #define M5B_DPLL_MULT_19		(125 << 12)
267 #define M4_DPLL_MULT_12			(133 << 12)
273 #define M4_DPLL_MULT_13			(399 << 12)
274 #define M4_DPLL_DIV_13			(12 << 8)
279 #define M4_DPLL_MULT_19			(145 << 12)
288 #define M3_DPLL_MULT_12			(55 << 12)
293 #define M3_DPLL_MULT_13			(76 << 12)
298 #define M3_DPLL_MULT_19			(17 << 12)
307 #define M2_DPLL_MULT_12		        (55 << 12)
316 #define M2_DPLL_MULT_13		        (76 << 12)
322 #define M2_DPLL_MULT_19		        (17 << 12)
329 #define MB_DPLL_MULT			(1 << 12)
354 #define MI_DPLL_MULT_12			(55 << 12)
364 #define MII_DPLL_MULT_12		(50 << 12)
369 #define MII_DPLL_MULT_13		(300 << 12)
370 #define MII_DPLL_DIV_13			(12 << 8)
376 #define MIII_DPLL_MULT_12		(133 << 12)
381 #define MIII_DPLL_MULT_13		(266 << 12)
382 #define MIII_DPLL_DIV_13		(12 << 8)