Lines Matching +full:0 +full:x558
26 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
28 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
29 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
30 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
31 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
32 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
33 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
34 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
35 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
36 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
37 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
38 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
39 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
40 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
41 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
42 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
43 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
44 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
45 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
46 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
47 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
48 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
49 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
50 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
51 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
52 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
53 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
54 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
55 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
56 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
59 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
60 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
61 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
62 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
63 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
64 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
65 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
66 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
67 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
68 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
69 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
70 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
71 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
72 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
73 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
74 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
77 #define DM816X_DM_ALWON_BASE 0x1400
78 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
79 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
80 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
81 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
82 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
83 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
84 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
85 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
86 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
87 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
88 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
95 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
97 #define DM81XX_CM_DEFAULT_OFFSET 0x500
98 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
99 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET)
217 .rev_offs = 0x74,
218 .sysc_offs = 0x78,
253 .rev_offs = 0x50,
254 .sysc_offs = 0x54,
255 .syss_offs = 0x58,
333 .rev_offs = 0x0,
334 .sysc_offs = 0x10,
335 .syss_offs = 0x14,
371 .rev_offs = 0x0,
372 .sysc_offs = 0x10,
373 .syss_offs = 0x90,
427 .rev_offs = 0x0000,
428 .sysc_offs = 0x0010,
429 .syss_offs = 0x0014,
457 .rev_offs = 0x0000,
458 .sysc_offs = 0x0010,
459 .syss_offs = 0x0114,
578 .rev_offs = 0x0,
579 .sysc_offs = 0x10,
580 .syss_offs = 0x14,
615 .rev_offs = 0x0,
616 .sysc_offs = 0x10,
670 .rev_offs = 0x0000,
671 .sysc_offs = 0x0010,
672 .syss_offs = 0x0014,
786 .rev_offs = 0x0,
787 .sysc_offs = 0x4,
866 .rev_offs = 0x00fc,
867 .sysc_offs = 0x1100,
899 .rev_offs = 0x0,
900 .sysc_offs = 0x110,
901 .syss_offs = 0x114,
1017 .rev_offs = 0x0,
1018 .sysc_offs = 0x110,
1019 .syss_offs = 0x114,
1113 .rev_offs = 0x000,
1114 .sysc_offs = 0x010,
1115 .syss_offs = 0x014,
1148 .rev_offs = 0x000,
1149 .sysc_offs = 0x010,
1150 .syss_offs = 0x014,