Lines Matching +full:function +full:- +full:off

1 // SPDX-License-Identifier: GPL-2.0-only
8 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
17 * to the Cortex-A9 processor must be asserted by the external
24 * ----------------------------------------------
26 * ON(Inactive) OFF ON(Inactive)
27 * OFF OFF CSWR
28 * OFF OFF OSWR
29 * OFF OFF OFF(Device OFF *TBD)
30 * ----------------------------------------------
33 * and first to wake-up when MPUSS low power states are excercised
48 #include <asm/hardware/cache-l2x0.h>
53 #include "omap4-sar-layout.h"
60 #include "prm-regbits-44xx.h"
75 * struct cpu_pm_ops - CPU pm operations
76 * @finish_suspend: CPU suspend finisher function pointer
77 * @resume: CPU resume function pointer
78 * @scu_prepare: CPU Snoop Control program function pointer
79 * @hotplug_restart: CPU restart function pointer
116 * used for OFF or DORMANT wakeup.
122 if (pm_info->wkup_sar_addr) in set_cpu_wakeup_addr()
123 writel_relaxed(addr, pm_info->wkup_sar_addr); in set_cpu_wakeup_addr()
148 if (pm_info->scu_sar_addr) in scu_pwrst_prepare()
149 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); in scu_pwrst_prepare()
187 if (pm_info->l2x0_sar_addr) in l2x0_pwrst_prepare()
188 writel_relaxed(save_state, pm_info->l2x0_sar_addr); in l2x0_pwrst_prepare()
193 * in every restore MPUSS OFF path.
213 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
214 * The purpose of this function is to manage low power programming
222 * 0 - Nothing lost and no need to save: MPUSS INACTIVE
223 * 1 - CPUx L1 and logic lost: MPUSS CSWR
224 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
225 * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
234 return -ENXIO; in omap4_enter_lowpower()
254 * CPUx OSWR equivalent to CPUX OFF and hence not supported in omap4_enter_lowpower()
257 return -ENXIO; in omap4_enter_lowpower()
264 * In MPUSS OSWR or device OFF, interrupt controller contest is lost. in omap4_enter_lowpower()
272 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); in omap4_enter_lowpower()
273 pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state); in omap4_enter_lowpower()
283 * Call low level function with targeted low power state. in omap4_enter_lowpower()
303 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); in omap4_enter_lowpower()
321 return -ENXIO; in omap4_hotplug_cpu()
324 power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm, in omap4_hotplug_cpu()
330 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); in omap4_hotplug_cpu()
331 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); in omap4_hotplug_cpu()
336 * CPU never returns back if targeted power state is OFF mode. in omap4_hotplug_cpu()
342 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); in omap4_hotplug_cpu()
371 return -ENODEV; in omap4_mpuss_init()
377 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; in omap4_mpuss_init()
379 pm_info->wkup_sar_addr = sar_base + in omap4_mpuss_init()
382 pm_info->wkup_sar_addr = sar_base + in omap4_mpuss_init()
384 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; in omap4_mpuss_init()
386 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); in omap4_mpuss_init()
387 if (!pm_info->pwrdm) { in omap4_mpuss_init()
389 return -ENODEV; in omap4_mpuss_init()
393 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); in omap4_mpuss_init()
397 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); in omap4_mpuss_init()
401 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; in omap4_mpuss_init()
403 pm_info->wkup_sar_addr = sar_base + in omap4_mpuss_init()
406 pm_info->wkup_sar_addr = sar_base + in omap4_mpuss_init()
408 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; in omap4_mpuss_init()
411 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); in omap4_mpuss_init()
412 if (!pm_info->pwrdm) { in omap4_mpuss_init()
414 return -ENODEV; in omap4_mpuss_init()
418 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); in omap4_mpuss_init()
422 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); in omap4_mpuss_init()
427 return -ENODEV; in omap4_mpuss_init()