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23 #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST		0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST		0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0
38 #define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700
39 #define DRA7XX_CM_CORE_AON_RTC_INST		0x0740
40 #define DRA7XX_CM_CORE_AON_VPE_INST		0x0760
43 #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
44 #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000
45 #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000
46 #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040
47 #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000
48 #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000
49 #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000
50 #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000
51 #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000
52 #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000
53 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000