1 // SPDX-License-Identifier: GPL-2.0-only
3  * DPLL + CORE_CLK composite clock functions
5  * Copyright (C) 2005-2008 Texas Instruments, Inc.
6  * Copyright (C) 2004-2010 Nokia Corporation
9  * Richard Woodruff <r-woodruff2@ti.com>
15  * XXX The DPLL and CORE clocks should be split into two separate clock
26 #include "clock.h"
30 #include "cm-regbits-24xx.h"
38  * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
44  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
49  * struct clk *dpll_ck, which is a composite clock of dpll_ck and
82 		high = curr_prcm_set->dpll_speed * 2;  in omap2_dpllcore_round_rate()
83 		low = curr_prcm_set->dpll_speed;  in omap2_dpllcore_round_rate()
85 		high = curr_prcm_set->dpll_speed;  in omap2_dpllcore_round_rate()
86 		low = curr_prcm_set->dpll_speed / 2;  in omap2_dpllcore_round_rate()
113 	u32 cur_rate, low, mult, div, valid_rate, done_rate;  in omap2_reprogram_dpllcore()  local
119 	mult = omap2xxx_cm_get_core_clk_src();  in omap2_reprogram_dpllcore()
121 	if ((rate == (cur_rate / 2)) && (mult == 2)) {  in omap2_reprogram_dpllcore()
123 	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {  in omap2_reprogram_dpllcore()
128 			return -EINVAL;  in omap2_reprogram_dpllcore()
130 		if (mult == 1)  in omap2_reprogram_dpllcore()
131 			low = curr_prcm_set->dpll_speed;  in omap2_reprogram_dpllcore()
133 			low = curr_prcm_set->dpll_speed / 2;  in omap2_reprogram_dpllcore()
135 		dd = clk->dpll_data;  in omap2_reprogram_dpllcore()
137 			return -EINVAL;  in omap2_reprogram_dpllcore()
140 			omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);  in omap2_reprogram_dpllcore()
141 		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |  in omap2_reprogram_dpllcore()
142 					   dd->div1_mask);  in omap2_reprogram_dpllcore()
143 		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);  in omap2_reprogram_dpllcore()
148 			mult = ((rate / 2) / 1000000);  in omap2_reprogram_dpllcore()
152 			mult = (rate / 1000000);  in omap2_reprogram_dpllcore()
155 		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));  in omap2_reprogram_dpllcore()
156 		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));  in omap2_reprogram_dpllcore()
161 		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */  in omap2_reprogram_dpllcore()
180  * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
185  * only be called once.  No return value.  XXX If the clock
192 	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");  in omap2xxx_clkt_dpllcore_init()