Lines Matching +full:emc +full:- +full:mode +full:- +full:4

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * arch/arm/mach-lpc32xx/suspend.S
39 	stmfd	r0!, {r3 - r7, sp, lr}
44 	ldr	EMCBASE_REG, [WORK1_REG, #4]
63 	@ Setup self-refresh with support for manual exit of
64 	@ self-refresh mode
70 	@ Wait for self-refresh acknowledge, clocks to the DRAM device
71 	@ will automatically stop on start of self-refresh
76 	bne	3b @ Branch until self-refresh mode starts
78 	@ Enter direct-run mode from run mode
82 	@ Safe disable of DRAM clock in EMC block, prevents DDR sync
95 	@ Enter stop mode until an enabled event occurs
108 4:
111 	bne	4b
113 	@ Re-enter run mode with self-refresh flag cleared, but no DRAM
114 	@ update yet. DRAM is still in self-refresh
118 	@ Restore original DRAM clock mode to restore DRAM clocks
122 	@ Clear self-refresh mode
129 	@ Wait for EMC to clear self-refresh mode
133 	bne	5b @ Branch until self-refresh has exited
137 	ldmfd	r0!, {r3 - r7, sp, pc}
148 	.word	. - lpc32xx_sys_suspend