Lines Matching +full:0 +full:x01c00000
27 #define DA8XX_TPCC_BASE 0x01c00000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
31 #define DA8XX_I2C0_BASE 0x01c22000
32 #define DA8XX_RTC_BASE 0x01c23000
33 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
34 #define DA8XX_MMCSD0_BASE 0x01c40000
35 #define DA8XX_SPI0_BASE 0x01c41000
36 #define DA830_SPI1_BASE 0x01e12000
37 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
38 #define DA850_SATA_BASE 0x01e18000
39 #define DA850_MMCSD1_BASE 0x01e1b000
40 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
41 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
42 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
43 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
44 #define DA8XX_I2C1_BASE 0x01e28000
45 #define DA850_TPCC1_BASE 0x01e30000
46 #define DA850_TPTC2_BASE 0x01e38000
47 #define DA850_SPI1_BASE 0x01f0e000
48 #define DA8XX_DDR2_CTL_BASE 0xb0000000
50 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
51 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
52 #define DA8XX_EMAC_RAM_OFFSET 0x0000