Lines Matching refs:r6
273 ldr r6, =(_end) @ Cover whole kernel
274 sub r6, r6, r5 @ Minimum size of region to map
275 clz r6, r6 @ Region size must be 2^N...
276 rsb r6, r6, #31 @ ...so round up region size
277 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
278 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
295 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
297 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
306 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
308 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
310 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
320 ldr r6, =(_exiprom) @ ROM end
321 sub r6, r6, r0 @ Minimum size of region to map
322 clz r6, r6 @ Region size must be 2^N...
323 rsb r6, r6, #31 @ ...so round up region size
324 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
325 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
327 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
329 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
343 ldr r6, =(_exiprom) @ ROM end
344 sub r6, r6, #1
345 bic r6, r6, #(PMSAv8_MINALIGN - 1)
348 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
353 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
357 ldr r6, =KERNEL_END
358 sub r6, r6, #1
359 bic r6, r6, #(PMSAv8_MINALIGN - 1)
362 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
365 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
367 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
371 ldr r6, =KERNEL_START
373 cmp r6, r5
374 movcs r6, r5
376 ldr r6, =KERNEL_START
378 cmp r6, #0
382 sub r6, r6, #1
383 bic r6, r6, #(PMSAv8_MINALIGN - 1)
386 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
389 AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
391 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
397 ldr r6, =(_exiprom)
398 cmp r5, r6
399 movcc r5, r6
403 mov r6, #0xffffffff
404 bic r6, r6, #(PMSAv8_MINALIGN - 1)
407 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
410 AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
412 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
417 ldr r6, =KERNEL_END
418 cmp r5, r6
419 movcs r5, r6
421 ldr r6, =KERNEL_START
423 cmp r6, r0
424 movcc r6, r0
426 sub r6, r6, #1
427 bic r6, r6, #(PMSAv8_MINALIGN - 1)
430 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
439 str r6, [r12, #PMSAv8_RLAR_A(0)]
442 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4
456 ldr r6, [r7] @ get secondary_data.mpu_rgn_info
478 ldr r4, [r6, #MPU_RNG_INFO_USED]
480 add r3, r6, #MPU_RNG_INFO_RNGS
492 ldr r6, [r3, #MPU_RGN_DRSR]
495 setup_region r0, r5, r6, PMSAv7_DATA_SIDE
497 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
508 ldr r4, [r6, #MPU_RNG_INFO_USED]
513 add r3, r6, #MPU_RNG_INFO_RNGS
524 ldr r6, [r3, #MPU_RGN_PRLAR]
527 mcr p15, 0, r6, c6, c3, 1 @ PRLAR