include/asm/pgtable-2level.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  arch/arm/include/asm/pgtable-2level.h
5  *  Copyright (C) 1995-2002 Russell King
13  * Hardware-wise, we have a two level page table structure, where the first
15  * is one 32-bit word.  Most of the bits in the second level entry are used
16  * by hardware, and there aren't any "accessed" and "dirty" bits.
19  * be wrapped to fit a two level page table structure easily - using the PGD
23  * Therefore, we tweak the implementation slightly - we tell Linux that we
25  * hardware pointers to the second level.)  The second level contains two
26  * hardware PTE tables arranged contiguously, preceded by Linux versions
34  * +--------+
35  * |        |       +------------+ +0
36  * +- - - - +       | Linux pt 0 |
37  * |        |       +------------+ +1024
38  * +--------+ +0    | Linux pt 1 |
39  * |        |-----> +------------+ +2048
40  * +- - - - + +4    |  h/w pt 0  |
41  * |        |-----> +------------+ +3072
42  * +--------+ +8    |  h/w pt 1  |
43  * |        |       +------------+ +4096
50  * The "dirty" bit is emulated by only granting hardware write permission
54  * For the hardware to notice the permission change, the TLB entry must
65  * by clearing the hardware PTE.  Currently Linux does not flush the TLB
81  * PMD_SHIFT determines the size of the area a second-level page table can map
82  * PGDIR_SHIFT determines what a third-level page table entry can map
88 #define PMD_MASK		(~(PMD_SIZE-1))
90 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
97 #define SECTION_MASK		(~(SECTION_SIZE-1))
104 #define SUPERSECTION_MASK	(~(SUPERSECTION_SIZE-1))
111  * We keep two sets of PTEs - the hardware and the linux version.
113  * onto the hardware tables, and allows us to have YOUNG and DIRTY
116  * The PTE table pointer refers to the hardware entries; the "Linux"
134  * pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B
138  * MT type		Pre-ARMv6	ARMv6+ type / cacheable status
140  * BUFFERABLE		Bufferable	Normal memory / non-cacheable
146  * DEV_NONSHARED	Uncached	Device memory (non-shared)
147  * DEV_WC		Bufferable	Normal memory / non-cacheable
152  * - reads can be repeated with no side effects
153  * - repeated reads return the last value written
154  * - reads can fetch additional locations without side effects
155  * - writes can be repeated (in certain cases) with no side effects
156  * - writes can be merged before accessing the target
157  * - unaligned accesses can be supported
160  * - no access speculation
161  * - no repetition (eg, on return from an exception)
162  * - number, order and size of accesses are maintained
163  * - unaligned accesses are "unpredictable"