Lines Matching full:h4
178 my ($h0,$h1,$h2,$h3,$h4,$r0,$r1,$r2,$r3)=map("r$_",(4..12));
201 ldmia $ctx!,{$h0-$h4} @ load hash value
211 adcs $r3,$r3,$h4,lsl#8
215 adc $len,$len,$h4,lsr#24
224 movne $h4,$len
241 addhi $h4,$h4,#1 @ 1<<128
280 addhi $h4,$h4,#1 @ padbit
301 adc $h4,$h4,#0
303 umlal r2,r3,$h4,$s1
312 mul r0,$s2,$h4
319 mul r2,$s3,$h4
331 mul $h4,$r0,$h4
340 add $h4,$h4,r3 @ h4+=d3>>32
342 and r1,$h4,#-4
343 and $h4,$h4,#3
349 adc $h4,$h4,#0
356 stmdb $ctx,{$h0-$h4} @ store the result
372 my ($h0,$h1,$h2,$h3,$h4,$g0,$g1,$g2,$g3)=map("r$_",(3..11));
382 ldmia $ctx,{$h0-$h4}
393 adcs $g3,$g3,$h4,lsl#8
395 adc $g4,$g4,$h4,lsr#24
404 movne $h4,$g4
411 adc $g4,$h4,#0
496 my ($D0,$D1,$D2,$D3,$D4, $H0,$H1,$H2,$H3,$H4) = map("q$_",(5..14));
548 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
549 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
550 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
551 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
552 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
588 @ H0>>+H1>>+H2>>+H3>>+H4
589 @ H3>>+H4>>*5+H0>>+H1
602 @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
609 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
619 @ 5*H4 - by 5*5 52-bit addends, or 57 bits. But when hashing the
621 @ 5*H4 by 5*5*3, or 59[!] bits. How is this relevant? vmlal.u32
627 @ one has to watch for H2 (which is narrower than H0) and 5*H4
637 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
654 vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
663 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
801 vmov.32 $H4#lo[0],$padbit
811 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
816 vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
845 vmov.i32 $H4,#1<<24 @ padbit, yes, always
860 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
897 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
898 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
899 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
900 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
901 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
916 vadd.i32 $H4#lo,$H4#lo,$D4#lo
917 vmull.u32 $D4,$H4#hi,${R0}[1]
919 vmlal.u32 $D0,$H4#hi,${S1}[1]
930 vmlal.u32 $D1,$H4#hi,${S2}[1]
937 vmlal.u32 $D2,$H4#hi,${S3}[1]
939 vmlal.u32 $D3,$H4#hi,${S4}[1]
953 vmlal.u32 $D4,$H4#lo,${R0}[0]
959 vmlal.u32 $D0,$H4#lo,${S1}[0]
967 vmlal.u32 $D1,$H4#lo,${S2}[0]
974 vmlal.u32 $D3,$H4#lo,${S4}[0]
976 vmlal.u32 $D2,$H4#lo,${S3}[0]
979 vmov.i32 $H4,#1<<24 @ padbit, yes, always
994 @ inp[0:3] previously loaded to $H0-$H3 and smashed to $H0-$H4.
1000 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1002 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
1022 vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
1037 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
1057 vadd.i32 $H4#hi,$H4#lo,$D4#lo
1071 vadd.i32 $H4#lo,$H4#lo,$D4#lo
1072 vmull.u32 $D4,$H4#hi,$R0
1074 vmlal.u32 $D0,$H4#hi,$S1
1087 vmlal.u32 $D1,$H4#hi,$S2
1098 vmlal.u32 $D2,$H4#hi,$S3
1100 vmlal.u32 $D3,$H4#hi,$S4
1120 vmlal.u32 $D4,$H4#lo,$R0
1122 vmlal.u32 $D0,$H4#lo,$S1
1135 vmlal.u32 $D1,$H4#lo,$S2
1142 vmlal.u32 $D2,$H4#lo,$S3
1144 vmlal.u32 $D3,$H4#lo,$S4
1169 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1182 vadd.i64 $D0,$D0,$T0 @ h4 -> h0
1190 vadd.i64 $D4,$D4,$T1 @ h3 -> h4