Lines Matching full:h3
178 my ($h0,$h1,$h2,$h3,$h4,$r0,$r1,$r2,$r3)=map("r$_",(4..12));
209 adcs $r2,$r2,$h3,lsl#14
210 mov $r3,$h3,lsr#18
221 movne $h3,$r3
297 adcs $h3,$h3,r3
304 umlal r0,r1,$h3,$s1
308 umlal r2,r3,$h3,$s2
321 umlal r0,r1,$h3,$s3
323 umlal r2,r3,$h3,$r0
337 adds $h3,r2,r1 @ d3+=d2>>32
348 adcs $h3,$h3,#0
372 my ($h0,$h1,$h2,$h3,$h4,$g0,$g1,$g2,$g3)=map("r$_",(3..11));
391 adcs $g2,$g2,$h3,lsl#14
392 mov $g3,$h3,lsr#18
402 movne $h3,$g3
410 adcs $g3,$h3,#0
432 movne $h3,$g3
438 adc $h3,$h3,$g3
445 rev $h3,$h3
450 str $h3,[$mac,#12]
458 strb $h3,[$mac,#12]
459 mov $h3,$h3,lsr#8
467 strb $h3,[$mac,#13]
468 mov $h3,$h3,lsr#8
476 strb $h3,[$mac,#14]
477 mov $h3,$h3,lsr#8
482 strb $h3,[$mac,#15]
496 my ($D0,$D1,$D2,$D3,$D4, $H0,$H1,$H2,$H3,$H4) = map("q$_",(5..14));
548 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
549 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
550 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
551 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
552 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
588 @ H0>>+H1>>+H2>>+H3>>+H4
589 @ H3>>+H4>>*5+H0>>+H1
602 @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
609 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
637 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
655 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
663 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
800 vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
807 vrev32.8 $H3,$H3
811 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
812 vshl.u32 $H3#lo,$H3#lo,#18
814 vsri.u32 $H3#lo,$H2#lo,#14
818 vbic.i32 $H3#lo,#0xfc000000
824 vadd.i32 $H3#hi,$H3#lo,$D3#lo
846 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
848 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
856 vrev32.8 $H3,$H3
860 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
861 vshl.u32 $H3,$H3,#18
863 vsri.u32 $H3,$H2,#14
866 vbic.i32 $H3,#0xfc000000
897 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
898 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
899 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
900 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
901 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
910 vadd.i32 $H3#lo,$H3#lo,$D3#lo
911 vmull.u32 $D3,$H3#hi,${R0}[1]
925 vmlal.u32 $D4,$H3#hi,${R1}[1]
927 vmlal.u32 $D0,$H3#hi,${S2}[1]
936 vmlal.u32 $D1,$H3#hi,${S3}[1]
943 vmlal.u32 $D2,$H3#hi,${S4}[1]
945 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
951 vmlal.u32 $D3,$H3#lo,${R0}[0]
960 vmlal.u32 $D4,$H3#lo,${R1}[0]
965 vmlal.u32 $D0,$H3#lo,${S2}[0]
973 vmlal.u32 $D1,$H3#lo,${S3}[0]
981 vmlal.u32 $D2,$H3#lo,${S4}[0]
983 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
989 vrev32.8 $H3,$H3
994 @ inp[0:3] previously loaded to $H0-$H3 and smashed to $H0-$H4.
1000 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1002 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
1004 vshl.u32 $H3,$H3,#18
1012 vsri.u32 $H3,$H2,#14
1019 vbic.i32 $H3,#0xfc000000
1024 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
1037 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
1055 vadd.i32 $H3#hi,$H3#lo,$D3#lo
1067 vadd.i32 $H3#lo,$H3#lo,$D3#lo
1068 vmull.u32 $D3,$H3#hi,$R0
1079 vmlal.u32 $D4,$H3#hi,$R1
1084 vmlal.u32 $D0,$H3#hi,$S2
1097 vmlal.u32 $D1,$H3#hi,$S3
1106 vmlal.u32 $D2,$H3#hi,$S4
1118 vmlal.u32 $D3,$H3#lo,$R0
1127 vmlal.u32 $D4,$H3#lo,$R1
1132 vmlal.u32 $D0,$H3#lo,$S2
1141 vmlal.u32 $D1,$H3#lo,$S3
1150 vmlal.u32 $D2,$H3#lo,$S4
1169 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1183 vadd.i64 $D3,$D3,$T1 @ h2 -> h3
1190 vadd.i64 $D4,$D4,$T1 @ h3 -> h4