Lines Matching +full:0 +full:x250
15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
26 reg = <0x0 0x0>;
46 reg = <0xd8140000 0x10000>;
55 reg = <0xD8150000 0x10000>;
61 reg = <0xd8110000 0x10000>;
70 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
83 #clock-cells = <0>;
89 #clock-cells = <0>;
92 reg = <0x200>;
96 #clock-cells = <0>;
99 reg = <0x204>;
103 #clock-cells = <0>;
106 reg = <0x208>;
110 #clock-cells = <0>;
113 reg = <0x20c>;
117 #clock-cells = <0>;
120 reg = <0x210>;
124 #clock-cells = <0>;
127 reg = <0x214>;
131 #clock-cells = <0>;
134 reg = <0x218>;
138 #clock-cells = <0>;
141 divisor-reg = <0x300>;
145 #clock-cells = <0>;
148 divisor-reg = <0x304>;
152 #clock-cells = <0>;
155 divisor-reg = <0x320>;
159 #clock-cells = <0>;
162 divisor-reg = <0x310>;
166 #clock-cells = <0>;
169 enable-reg = <0x254>;
174 #clock-cells = <0>;
177 enable-reg = <0x254>;
182 #clock-cells = <0>;
185 enable-reg = <0x254>;
190 #clock-cells = <0>;
193 enable-reg = <0x254>;
198 #clock-cells = <0>;
201 divisor-reg = <0x350>;
202 enable-reg = <0x250>;
207 #clock-cells = <0>;
210 divisor-reg = <0x330>;
211 divisor-mask = <0x3f>;
212 enable-reg = <0x250>;
213 enable-bit = <0>;
220 reg = <0xd8051700 0x200>;
225 reg = <0xd8050400 0x100>;
231 reg = <0xd8220000 0x100>;
237 reg = <0xd8130100 0x28>;
243 reg = <0xd8007900 0x200>;
249 reg = <0xd8007b00 0x200>;
255 reg = <0xd8008d00 0x200>;
261 reg = <0xd8200000 0x1040>;
269 reg = <0xd82b0000 0x1040>;
277 reg = <0xd8210000 0x1040>;
285 reg = <0xd82c0000 0x1040>;
293 reg = <0xd8100000 0x10000>;
299 reg = <0xd800a000 0x1000>;
308 reg = <0xd8004000 0x100>;