Lines Matching +full:0 +full:x58000000
40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
112 clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
113 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
114 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
121 reg = <0x44000000 0x1000>,
122 <0x44800000 0x2000>,
123 <0x45000000 0x1000>;
140 clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
144 ranges = <0 0x48210000 0x1f0000>;
157 reg = <0x50000000 4>,
158 <0x50000010 4>,
159 <0x50000014 4>;
166 clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
170 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
171 <0x00000000 0x00000000 0x40000000>; /* data */
175 reg = <0x50000000 0x1000>;
194 reg = <0x52000000 0x4>,
195 <0x52000010 0x4>;
208 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
212 ranges = <0 0x52000000 0x1000000>;
226 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
230 ranges = <0x0 0x54000000 0x1000000>;
239 reg = <0x55082000 0x4>,
240 <0x55082010 0x4>,
241 <0x55082014 0x4>;
249 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
253 ranges = <0x0 0x55082000 0x100>;
257 mmu_ipu: mmu@0 {
259 reg = <0x0 0x100>;
261 #iommu-cells = <0>;
268 reg = <0x4012c000 0x4>,
269 <0x4012c010 0x4>;
276 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
280 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
281 <0x4902c000 0x4902c000 0x1000>; /* L3 */
288 reg = <0x4e000000 0x4>,
289 <0x4e000010 0x4>;
294 ranges = <0x0 0x4e000000 0x2000000>;
298 dmm@0 {
300 reg = <0 0x800>;
307 reg = <0x4c000000 0x4>;
309 clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
314 ranges = <0x0 0x4c000000 0x1000000>;
316 emif1: emif@0 {
318 reg = <0 0x100>;
329 reg = <0x4d000000 0x4>;
331 clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
336 ranges = <0x0 0x4d000000 0x1000000>;
338 emif2: emif@0 {
340 reg = <0 0x100>;
351 ti,bootreg = <&scm_conf 0x304 0>;
353 resets = <&prm_tesla 0>;
354 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
362 reg = <0x55020000 0x10000>;
365 resets = <&prm_core 0>, <&prm_core 1>;
366 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
374 reg = <0x4b501080 0x4>,
375 <0x4b501084 0x4>,
376 <0x4b501088 0x4>;
386 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
390 ranges = <0x0 0x4b501000 0x1000>;
392 aes1: aes@0 {
394 reg = <0 0xa0>;
403 reg = <0x4b701080 0x4>,
404 <0x4b701084 0x4>,
405 <0x4b701088 0x4>;
415 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
419 ranges = <0x0 0x4b701000 0x1000>;
421 aes2: aes@0 {
423 reg = <0 0xa0>;
432 reg = <0x4b100100 0x4>,
433 <0x4b100110 0x4>,
434 <0x4b100114 0x4>;
443 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
447 ranges = <0x0 0x4b100000 0x1000>;
449 sham: sham@0 {
451 reg = <0 0x300>;
461 #address-cells = <0>;
462 #size-cells = <0>;
463 ti,tranxdone-status-mask = <0x80>;
474 #address-cells = <0>;
475 #size-cells = <0>;
476 ti,tranxdone-status-mask = <0x80000000>;
486 reg = <0x5600fe00 0x4>,
487 <0x5600fe10 0x4>;
498 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
502 ranges = <0 0x56000000 0x2000000>;
504 gpu@0 {
506 reg = <0x0 0x2000000>; /* 32MB */
517 reg = <0x58000000 4>,
518 <0x58000014 4>;
522 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
529 ranges = <0 0x58000000 0x1000000>;
531 dss: dss@0 {
533 reg = <0 0x80>;
539 ranges = <0 0 0x1000000>;
543 reg = <0x1000 0x4>,
544 <0x1010 0x4>,
545 <0x1014 0x4>;
563 ranges = <0 0x1000 0x1000>;
565 dispc@0 {
567 reg = <0 0x1000>;
576 reg = <0x2000 0x4>,
577 <0x2010 0x4>,
578 <0x2014 0x4>;
591 ranges = <0 0x2000 0x1000>;
593 rfbi: encoder@0 {
594 reg = <0 0x1000>;
603 reg = <0x3000 0x4>;
609 ranges = <0 0x3000 0x1000>;
611 venc: encoder@0 {
613 reg = <0 0x1000>;
622 reg = <0x4000 0x4>,
623 <0x4010 0x4>,
624 <0x4014 0x4>;
636 ranges = <0 0x4000 0x1000>;
638 dsi1: encoder@0 {
640 reg = <0 0x200>,
641 <0x200 0x40>,
642 <0x300 0x20>;
651 #size-cells = <0>;
657 reg = <0x5000 0x4>,
658 <0x5010 0x4>,
659 <0x5014 0x4>;
671 ranges = <0 0x5000 0x1000>;
673 dsi2: encoder@0 {
675 reg = <0 0x200>,
676 <0x200 0x40>,
677 <0x300 0x20>;
686 #size-cells = <0>;
692 reg = <0x6000 0x4>,
693 <0x6010 0x4>;
707 ranges = <0 0x6000 0x2000>;
709 hdmi: encoder@0 {
711 reg = <0 0x200>,
712 <0x200 0x100>,
713 <0x300 0x100>,
714 <0x400 0x1000>;
730 reg = <0x5a05a400 0x4>,
731 <0x5a05a410 0x4>;
742 clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
746 ranges = <0x5a000000 0x5a000000 0x1000000>,
747 <0x5b000000 0x5b000000 0x1000000>;
763 reg = <0x300 0x100>;
764 #power-domain-cells = <0>;
769 reg = <0x400 0x100>;
771 #power-domain-cells = <0>;
776 reg = <0x500 0x100>;
777 #power-domain-cells = <0>;
782 reg = <0x600 0x100>;
783 #power-domain-cells = <0>;
788 reg = <0x700 0x100>;
790 #power-domain-cells = <0>;
795 reg = <0xf00 0x100>;
797 #power-domain-cells = <0>;
802 reg = <0x1000 0x100>;
803 #power-domain-cells = <0>;
808 reg = <0x1100 0x100>;
809 #power-domain-cells = <0>;
814 reg = <0x1200 0x100>;
815 #power-domain-cells = <0>;
820 reg = <0x1300 0x100>;
821 #power-domain-cells = <0>;
826 reg = <0x1400 0x100>;
827 #power-domain-cells = <0>;
832 reg = <0x1600 0x100>;
833 #power-domain-cells = <0>;
838 reg = <0x1700 0x100>;
839 #power-domain-cells = <0>;
844 reg = <0x1900 0x100>;
845 #power-domain-cells = <0>;
850 reg = <0x1100 0x40>;
851 #power-domain-cells = <0>;
856 reg = <0x1b00 0x40>;
865 timer@0 {