ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 		#clock-cells = <0>;
10 		compatible = "fixed-factor-clock";
12 		clock-mult = <1>;
13 		clock-div = <3>;
17 		#clock-cells = <0>;
18 		compatible = "fixed-factor-clock";
20 		clock-mult = <1>;
21 		clock-div = <5>;
26 		#clock-cells = <0>;
27 		compatible = "ti,omap3-dpll-clock";
30 		ti,low-power-stop;
35 		#clock-cells = <0>;
36 		compatible = "ti,divider-clock";
38 		ti,max-div = <31>;
40 		ti,index-starts-at-one;
44 		#clock-cells = <0>;
45 		compatible = "ti,composite-gate-clock";
47 		ti,bit-shift = <1>;
52 		#clock-cells = <0>;
53 		compatible = "fixed-factor-clock";
55 		clock-mult = <1>;
56 		clock-div = <3>;
60 		#clock-cells = <0>;
61 		compatible = "fixed-factor-clock";
63 		clock-mult = <1>;
64 		clock-div = <4>;
68 		#clock-cells = <0>;
69 		compatible = "fixed-factor-clock";
71 		clock-mult = <1>;
72 		clock-div = <6>;
76 		#clock-cells = <0>;
77 		compatible = "fixed-factor-clock";
79 		clock-mult = <1>;
80 		clock-div = <1>;
84 		#clock-cells = <0>;
85 		compatible = "fixed-factor-clock";
87 		clock-mult = <1>;
88 		clock-div = <2>;
92 		#clock-cells = <0>;
93 		compatible = "ti,composite-mux-clock";
99 		#clock-cells = <0>;
100 		compatible = "ti,composite-clock";
105 		#clock-cells = <0>;
106 		compatible = "ti,wait-gate-clock";
109 		ti,bit-shift = <0>;
113 		#clock-cells = <0>;
114 		compatible = "ti,gate-clock";
117 		ti,bit-shift = <0>;
121 		#clock-cells = <0>;
122 		compatible = "ti,gate-clock";
125 		ti,bit-shift = <1>;
129 		#clock-cells = <0>;
130 		compatible = "ti,wait-gate-clock";
133 		ti,bit-shift = <2>;
137 	clock@a18 {
140 		#clock-cells = <2>;
141 		#address-cells = <1>;
142 		#size-cells = <0>;
144 		usbtll_ick: clock-usbtll-ick@2 {
146 			#clock-cells = <0>;
147 			compatible = "ti,omap3-interface-clock";
148 			clock-output-names = "usbtll_ick";
153 	clock@a10 {
156 		#clock-cells = <2>;
157 		#address-cells = <1>;
158 		#size-cells = <0>;
160 		mmchs3_ick: clock-mmchs3-ick@30 {
162 			#clock-cells = <0>;
163 			compatible = "ti,omap3-interface-clock";
164 			clock-output-names = "mmchs3_ick";
169 	clock@a00 {
172 		#clock-cells = <2>;
173 		#address-cells = <1>;
174 		#size-cells = <0>;
176 		mmchs3_fck: clock-mmchs3-fck@30 {
178 			#clock-cells = <0>;
179 			compatible = "ti,wait-gate-clock";
180 			clock-output-names = "mmchs3_fck";
185 	clock@e00 {
188 		#clock-cells = <2>;
189 		#address-cells = <1>;
190 		#size-cells = <0>;
192 		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
194 			#clock-cells = <0>;
195 			compatible = "ti,dss-gate-clock";
196 			clock-output-names = "dss1_alwon_fck_3430es2";
198 			ti,set-rate-parent;
203 		#clock-cells = <0>;
204 		compatible = "ti,omap3-dss-interface-clock";
207 		ti,bit-shift = <0>;
211 		#clock-cells = <0>;
212 		compatible = "ti,gate-clock";
215 		ti,bit-shift = <1>;
219 		#clock-cells = <0>;
220 		compatible = "ti,dss-gate-clock";
223 		ti,bit-shift = <0>;
227 		#clock-cells = <0>;
228 		compatible = "ti,omap3-dss-interface-clock";
231 		ti,bit-shift = <0>;