Lines Matching +full:0 +full:x1400
9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
95 reg = <0x0b40>;
99 #clock-cells = <0>;
105 #clock-cells = <0>;
108 reg = <0x0b10>;
109 ti,bit-shift = <0>;
113 #clock-cells = <0>;
116 reg = <0x0a08>;
117 ti,bit-shift = <0>;
121 #clock-cells = <0>;
124 reg = <0x0a08>;
129 #clock-cells = <0>;
132 reg = <0x0a08>;
139 reg = <0xa18>;
142 #size-cells = <0>;
146 #clock-cells = <0>;
155 reg = <0xa10>;
158 #size-cells = <0>;
162 #clock-cells = <0>;
171 reg = <0xa00>;
174 #size-cells = <0>;
178 #clock-cells = <0>;
187 reg = <0xe00>;
190 #size-cells = <0>;
192 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
193 reg = <0>;
194 #clock-cells = <0>;
203 #clock-cells = <0>;
206 reg = <0x0e10>;
207 ti,bit-shift = <0>;
211 #clock-cells = <0>;
214 reg = <0x1400>;
219 #clock-cells = <0>;
222 reg = <0x1400>;
223 ti,bit-shift = <0>;
227 #clock-cells = <0>;
230 reg = <0x1410>;
231 ti,bit-shift = <0>;