Lines Matching +full:0 +full:x0b00

9 		#clock-cells = <0>;
12 		reg = <0x0b10>;
13 		ti,bit-shift = <0>;
17 		#clock-cells = <0>;
21 		reg = <0x0b40>;
26 		#clock-cells = <0>;
34 		#clock-cells = <0>;
37 		reg = <0x0b00>;
42 		#clock-cells = <0>;
45 		reg = <0x0b00>;
51 		reg = <0xa00>;
54 		#size-cells = <0>;
58 			#clock-cells = <0>;
66 			#clock-cells = <0>;
72 		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
73 			reg = <0>;
74 			#clock-cells = <0>;
83 		reg = <0xa40>;
86 		#size-cells = <0>;
90 			#clock-cells = <0>;
94 			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
99 			#clock-cells = <0>;
109 		#clock-cells = <0>;
115 		#clock-cells = <0>;
124 		reg = <0xa10>;
127 		#size-cells = <0>;
131 			#clock-cells = <0>;
139 			#clock-cells = <0>;
145 		ssi_ick: clock-ssi-ick-3430es1@0 {
146 			reg = <0>;
147 			#clock-cells = <0>;
155 			#clock-cells = <0>;
163 		#clock-cells = <0>;
171 		#clock-cells = <0>;
178 		reg = <0xe00>;
181 		#size-cells = <0>;
183 		dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
184 			reg = <0>;
185 			#clock-cells = <0>;
194 		#clock-cells = <0>;
197 		reg = <0x0e10>;
198 		ti,bit-shift = <0>;