Lines Matching +full:0 +full:x6e000000
34 #size-cells = <0>;
36 cpu@0 {
39 reg = <0x0>;
50 reg = <0x54000000 0x800000>;
85 reg = <0x68000000 0x10000>;
96 ranges = <0 0x48000000 0x1000000>;
100 reg = <0x2000 0x2000>;
103 ranges = <0 0x2000 0x2000>;
108 reg = <0x30 0x238>;
110 #size-cells = <0>;
115 pinctrl-single,function-mask = <0xff1f>;
120 reg = <0x270 0x330>;
123 ranges = <0 0x270 0x330>;
127 reg = <0x2b0 0x4>;
138 #size-cells = <0>;
148 reg = <0xa00 0x5c>;
150 #size-cells = <0>;
155 pinctrl-single,function-mask = <0xff1f>;
162 reg = <0x480a6044 0x4>,
163 <0x480a6048 0x4>,
164 <0x480a604c 0x4>;
175 ranges = <0 0x480a6000 0x2000>;
177 aes1: aes1@0 {
179 reg = <0 0x50>;
180 interrupts = <0>;
188 reg = <0x480c5044 0x4>,
189 <0x480c5048 0x4>,
190 <0x480c504c 0x4>;
201 ranges = <0 0x480c5000 0x2000>;
203 aes2: aes2@0 {
205 reg = <0 0x50>;
206 interrupts = <0>;
214 reg = <0x48306000 0x4000>;
219 #size-cells = <0>;
228 reg = <0x48004000 0x4000>;
232 #size-cells = <0>;
241 reg = <0x48320000 0x4>,
242 <0x48320004 0x4>;
250 ranges = <0x0 0x48320000 0x1000>;
252 counter32k: counter@0 {
254 reg = <0x0 0x20>;
262 reg = <0x48200000 0x1000>;
267 reg = <0x48056000 0x4>,
268 <0x4805602c 0x4>,
269 <0x48056028 0x4>;
287 ranges = <0 0x48056000 0x1000>;
289 sdma: dma-controller@0 {
291 reg = <0x0 0x1000>;
304 reg = <0x48310000 0x200>;
316 reg = <0x49050000 0x200>;
327 reg = <0x49052000 0x200>;
338 reg = <0x49054000 0x200>;
349 reg = <0x49056000 0x200>;
360 reg = <0x49058000 0x200>;
371 reg = <0x4806a000 0x2000>;
381 reg = <0x4806c000 0x400>;
391 reg = <0x49020000 0x400>;
401 reg = <0x48070000 0x80>;
404 #size-cells = <0>;
410 reg = <0x48072000 0x80>;
413 #size-cells = <0>;
419 reg = <0x48060000 0x80>;
422 #size-cells = <0>;
429 reg = <0x48094000 0x200>;
435 ti,mbox-tx = <0 0 0>;
436 ti,mbox-rx = <1 0 0>;
442 reg = <0x48098000 0x100>;
445 #size-cells = <0>;
462 reg = <0x4809a000 0x100>;
465 #size-cells = <0>;
477 reg = <0x480b8000 0x100>;
480 #size-cells = <0>;
492 reg = <0x480ba000 0x100>;
495 #size-cells = <0>;
504 reg = <0x480b2000 0x1000>;
511 reg = <0x4809c000 0x200>;
522 reg = <0x480b4000 0x200>;
531 reg = <0x480ad000 0x200>;
539 #iommu-cells = <0>;
541 reg = <0x480bd400 0x80>;
548 #iommu-cells = <0>;
550 reg = <0x5d000000 0x80>;
558 reg = <0x48314000 0x80>;
564 reg = <0x48074000 0xff>;
583 reg = <0x480a003c 0x4>,
584 <0x480a0040 0x4>,
585 <0x480a0044 0x4>;
595 ranges = <0 0x480a0000 0x2000>;
597 rng: rng@0 {
599 reg = <0x0 0x2000>;
606 reg = <0x49022000 0xff>,
607 <0x49028000 0xff>;
626 reg = <0x49024000 0xff>,
627 <0x4902a000 0xff>;
646 reg = <0x49026000 0xff>;
659 #sound-dai-cells = <0>;
665 reg = <0x48096000 0xff>;
684 reg = <0x480c3000 0x64>;
692 reg = <0x48318000 0x4>,
693 <0x48318010 0x4>,
694 <0x48318014 0x4>;
709 ranges = <0x0 0x48318000 0x1000>;
711 timer1: timer@0 {
713 reg = <0x0 0x80>;
723 reg = <0x49032000 0x4>,
724 <0x49032010 0x4>,
725 <0x49032014 0x4>;
740 ranges = <0x0 0x49032000 0x1000>;
742 timer2: timer@0 {
744 reg = <0 0x400>;
751 reg = <0x49034000 0x400>;
758 reg = <0x49036000 0x400>;
765 reg = <0x49038000 0x400>;
773 reg = <0x4903a000 0x400>;
781 reg = <0x4903c000 0x400>;
789 reg = <0x4903e000 0x400>;
798 reg = <0x49040000 0x400>;
806 reg = <0x48086000 0x400>;
814 reg = <0x48088000 0x400>;
822 reg = <0x48304000 0x4>,
823 <0x48304010 0x4>,
824 <0x48304014 0x4>;
839 ranges = <0x0 0x48304000 0x1000>;
841 timer12: timer@0 {
843 reg = <0 0x400>;
852 reg = <0x48062000 0x1000>;
859 reg = <0x48064000 0x400>;
867 reg = <0x48064400 0x400>;
874 reg = <0x48064800 0x400>;
882 reg = <0x6e000000 0x02d0>;
898 reg = <0x480ab400 0x4>,
899 <0x480ab404 0x4>,
900 <0x480ab408 0x4>;
916 ranges = <0x0 0x480ab000 0x1000>;
918 usb_otg_hs: usb@0 {
920 reg = <0 0x1000>;
931 reg = <0x48050000 0x200>;
942 reg = <0x48050400 0x400>;
951 reg = <0x4804fc00 0x200>,
952 <0x4804fe00 0x40>,
953 <0x4804ff00 0x20>;
962 #size-cells = <0>;
967 reg = <0x48050800 0x100>;
976 reg = <0x48050c00 0x100>;
990 reg = <0x48058000 0x1000>,
991 <0x48059000 0x1000>;
1005 reg = <0x4805a000 0x800>,
1006 <0x4805a800 0x800>;
1017 reg = <0x4805b000 0x800>,
1018 <0x4805b800 0x800>;
1035 timer@0 {