Lines Matching +full:0 +full:x009e0000
64 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
111 hdmi0: connector@0 {
124 tpd12s015: encoder@0 {
127 gpios = <0>, /* optional CT_CP_HPD */
128 <0>, /* optional LS_OE */
133 #size-cells = <0>;
135 port@0 {
136 reg = <0>;
138 tpd12s015_in: endpoint@0 {
146 tpd12s015_out: endpoint@0 {
154 #clock-cells = <0>;
163 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
164 DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */
170 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
171 DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
182 reg = <0x58>;
184 &dra7_pmx_core 0x418>;
393 reg = <0x60>;
400 reg = <0xe>;
412 #size-cells = <0>;
414 port@0 {
415 reg = <0>;
429 sn65hvs882: sn65hvs882@0 {
434 reg = <0>;
443 &dra7_pmx_core 0x248>;
468 ethphy0: ethernet-phy@0 {
469 reg = <0>;
520 pinctrl-0 = <&dcan1_pins_sleep>;
529 flash@0 {
532 reg = <0>;
543 partition@0 {
545 reg = <0x00000000 0x00040000>;
549 reg = <0x00040000 0x00100000>;
553 reg = <0x00140000 0x00080000>;
557 reg = <0x001c0000 0x00010000>;
561 reg = <0x001d0000 0x0010000>;
565 reg = <0x001e0000 0x0800000>;
569 reg = <0x009e0000 0x01620000>;
597 #size-cells = <0>;
599 port@0 {
600 reg = <0>;