Lines Matching +full:0 +full:x78000
20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
118 reg = <0x48241000 0x1000>,
119 <0x48240100 0x0100>;
127 reg = <0x48281000 0x1000>;
133 reg = <0x48240000 0x100>;
138 reg = <0x48240200 0x100>;
146 reg = <0x48240600 0x100>;
154 reg = <0x48242000 0x1000>;
162 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
171 reg = <0x44000000 0x400000>,
172 <0x44800000 0x400000>;
186 reg = <0x4c000000 0x4>;
188 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
193 ranges = <0x0 0x4c000000 0x1000000>;
195 emif: emif@0 {
197 reg = <0 0x1000000>;
206 reg = <0x49000000 0x4>;
208 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
212 ranges = <0x0 0x49000000 0x10000>;
214 edma: dma@0 {
216 reg = <0 0x10000>;
227 <&edma_tptc2 0>;
235 reg = <0x49800000 0x4>,
236 <0x49800010 0x4>;
242 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
246 ranges = <0x0 0x49800000 0x100000>;
248 edma_tptc0: dma@0 {
250 reg = <0 0x100000>;
258 reg = <0x49900000 0x4>,
259 <0x49900010 0x4>;
265 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
269 ranges = <0x0 0x49900000 0x100000>;
271 edma_tptc1: dma@0 {
273 reg = <0 0x100000>;
281 reg = <0x49a00000 0x4>,
282 <0x49a00010 0x4>;
288 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
292 ranges = <0x0 0x49a00000 0x100000>;
294 edma_tptc2: dma@0 {
296 reg = <0 0x100000>;
304 reg = <0x478102fc 0x4>,
305 <0x47810110 0x4>,
306 <0x47810114 0x4>;
316 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
320 ranges = <0x0 0x47810000 0x1000>;
322 mmc3: mmc@0 {
326 reg = <0x0 0x1000>;
333 reg = <0x53100100 0x4>,
334 <0x53100110 0x4>,
335 <0x53100114 0x4>;
344 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
348 ranges = <0x0 0x53100000 0x1000>;
350 sham: sham@0 {
352 reg = <0 0x300>;
353 dmas = <&edma 36 0>;
361 reg = <0x53501080 0x4>,
362 <0x53501084 0x4>,
363 <0x53501088 0x4>;
373 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
377 ranges = <0x0 0x53501000 0x1000>;
379 aes: aes@0 {
381 reg = <0 0xa0>;
383 dmas = <&edma 6 0>,
384 <&edma 5 0>;
391 reg = <0x53701030 0x4>,
392 <0x53701034 0x4>,
393 <0x53701038 0x4>;
403 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
407 ranges = <0 0x53701000 0x1000>;
409 des: des@0 {
411 reg = <0 0xa0>;
413 dmas = <&edma 34 0>,
414 <&edma 33 0>;
421 reg = <0x54426000 0x4>,
422 <0x54426004 0x4>;
432 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
438 ranges = <0x0 0x54400000 0x80000>;
440 pruss1: pruss@0 {
442 reg = <0x0 0x40000>;
447 pruss1_mem: memories@0 {
448 reg = <0x0 0x2000>,
449 <0x2000 0x2000>,
450 <0x10000 0x8000>;
457 reg = <0x26000 0x2000>;
460 ranges = <0x0 0x26000 0x2000>;
464 #size-cells = <0>;
467 reg = <0x30>;
468 #clock-cells = <0>;
477 reg = <0x32000 0x58>;
482 reg = <0x20000 0x2000>;
496 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
501 reg = <0x34000 0x3000>,
502 <0x22000 0x400>,
503 <0x22400 0x100>;
510 reg = <0x38000 0x3000>,
511 <0x24000 0x400>,
512 <0x24400 0x100>;
519 reg = <0x32400 0x90>;
524 #size-cells = <0>;
530 reg = <0x40000 0x40000>;
536 reg = <0x40000 0x1000>,
537 <0x42000 0x1000>;
543 reg = <0x66000 0x2000>;
546 ranges = <0x0 0x66000 0x2000>;
550 #size-cells = <0>;
553 reg = <0x30>;
554 #clock-cells = <0>;
563 reg = <0x72000 0x58>;
569 reg = <0x60000 0x2000>;
583 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
588 reg = <0x74000 0x1000>,
589 <0x62000 0x400>,
590 <0x62400 0x100>;
597 reg = <0x78000 0x1000>,
598 <0x64000 0x400>,
599 <0x64400 0x100>;
608 reg = <0x50000000 4>,
609 <0x50000010 4>,
610 <0x50000014 4>;
616 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
620 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
621 <0x00000000 0x00000000 0x40000000>; /* data */
625 dmas = <&edma 52 0>;
629 reg = <0x50000000 0x2000>;
645 reg = <0x47900000 0x4>,
646 <0x47900010 0x4>;
652 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
656 ranges = <0x0 0x47900000 0x1000>,
657 <0x30000000 0x30000000 0x4000000>;
659 qspi: spi@0 {
661 reg = <0 0x100>,
662 <0x30000000 0x4000000>;
667 #size-cells = <0>;
668 interrupts = <0 138 0x4>;
675 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
680 ranges = <0 0x40300000 0x40000>;
682 ocmcram: sram@0 {
684 reg = <0 0x40000>; /* 256k */
685 ranges = <0 0 0x40000>;
689 pm_sram_code: pm-code-sram@0 {
691 reg = <0x0 0x1000>;
697 reg = <0x1000 0x1000>;
705 reg = <0x5600fe00 0x4>,
706 <0x5600fe10 0x4>;
714 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
717 resets = <&prm_gfx 0>;
721 ranges = <0 0x56000000 0x1000000>;
723 gpu@0 {
725 reg = <0x0 0x10000>; /* 64kB */
738 reg = <0x300 0x100>;
739 #power-domain-cells = <0>;
744 reg = <0x400 0x100>;
745 #power-domain-cells = <0>;
751 reg = <0x500 0x100>;
752 #power-domain-cells = <0>;
757 reg = <0x600 0x100>;
758 #power-domain-cells = <0>;
763 reg = <0x700 0x100>;
764 #power-domain-cells = <0>;
769 reg = <0x800 0x100>;
771 #power-domain-cells = <0>;
776 reg = <0x2000 0x100>;
778 #power-domain-cells = <0>;
783 reg = <0x4000 0x100>;
792 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
793 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
795 timer@0 {
805 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
806 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
808 timer@0 {