Lines Matching +full:0 +full:x40300000
47 #size-cells = <0>;
48 cpu@0 {
52 reg = <0>;
87 opp-supported-hw = <0x06 0x0010>;
95 opp-supported-hw = <0x01 0x00FF>;
103 opp-supported-hw = <0x06 0x0020>;
111 opp-supported-hw = <0x01 0xFFFF>;
118 opp-supported-hw = <0x06 0x0040>;
125 opp-supported-hw = <0x01 0xFFFF>;
132 opp-supported-hw = <0x06 0x0080>;
139 opp-supported-hw = <0x01 0xFFFF>;
146 opp-supported-hw = <0x06 0x0100>;
153 opp-supported-hw = <0x04 0x0200>;
159 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
164 ranges = <0x0 0x4b000000 0x1000000>;
168 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
172 ranges = <0x0 0x140000 0xec0000>;
174 pmu@0 {
199 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
220 reg = <0x48200000 0x1000>;
225 reg = <0x49000000 0x4>;
227 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
231 ranges = <0x0 0x49000000 0x10000>;
233 edma: dma@0 {
235 reg = <0 0x10000>;
244 <&edma_tptc2 0>;
252 reg = <0x49800000 0x4>,
253 <0x49800010 0x4>;
259 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
263 ranges = <0x0 0x49800000 0x100000>;
265 edma_tptc0: dma@0 {
267 reg = <0 0x100000>;
275 reg = <0x49900000 0x4>,
276 <0x49900010 0x4>;
282 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
286 ranges = <0x0 0x49900000 0x100000>;
288 edma_tptc1: dma@0 {
290 reg = <0 0x100000>;
298 reg = <0x49a00000 0x4>,
299 <0x49a00010 0x4>;
305 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
309 ranges = <0x0 0x49a00000 0x100000>;
311 edma_tptc2: dma@0 {
313 reg = <0 0x100000>;
321 reg = <0x478102fc 0x4>,
322 <0x47810110 0x4>,
323 <0x47810114 0x4>;
333 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
337 ranges = <0x0 0x47810000 0x1000>;
339 mmc3: mmc@0 {
343 reg = <0x0 0x1000>;
350 reg = <0x47400000 0x4>,
351 <0x47400010 0x4>;
363 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
367 ranges = <0x0 0x47400000 0x8000>;
371 reg = <0x1300 0x100>;
374 #phy-cells = <0>;
379 reg = <0x1400 0x400>,
380 <0x1000 0x200>;
392 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
393 &cppi41dma 2 0 &cppi41dma 3 0
394 &cppi41dma 4 0 &cppi41dma 5 0
395 &cppi41dma 6 0 &cppi41dma 7 0
396 &cppi41dma 8 0 &cppi41dma 9 0
397 &cppi41dma 10 0 &cppi41dma 11 0
398 &cppi41dma 12 0 &cppi41dma 13 0
399 &cppi41dma 14 0 &cppi41dma 0 1
418 reg = <0x1b00 0x100>;
421 #phy-cells = <0>;
426 reg = <0x1c00 0x400>,
427 <0x1800 0x200>;
438 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
439 &cppi41dma 17 0 &cppi41dma 18 0
440 &cppi41dma 19 0 &cppi41dma 20 0
441 &cppi41dma 21 0 &cppi41dma 22 0
442 &cppi41dma 23 0 &cppi41dma 24 0
443 &cppi41dma 25 0 &cppi41dma 26 0
444 &cppi41dma 27 0 &cppi41dma 28 0
445 &cppi41dma 29 0 &cppi41dma 15 1
464 reg = <0x0000 0x1000>,
465 <0x2000 0x1000>,
466 <0x3000 0x1000>,
467 <0x4000 0x4000>;
482 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
487 ranges = <0 0x40300000 0x10000>;
489 ocmcram: sram@0 {
491 reg = <0 0x10000>; /* 64k */
492 ranges = <0 0 0x10000>;
496 pm_sram_code: pm-code-sram@0 {
498 reg = <0x0 0x1000>;
504 reg = <0x1000 0x1000>;
512 reg = <0x4c000000 0x4>;
514 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
519 ranges = <0x0 0x4c000000 0x1000000>;
521 emif: emif@0 {
523 reg = <0 0x1000000>;
532 reg = <0x50000000 4>,
533 <0x50000010 4>,
534 <0x50000014 4>;
540 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
544 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
545 <0x00000000 0x00000000 0x40000000>; /* data */
549 reg = <0x50000000 0x2000>;
551 dmas = <&edma 52 0>;
567 reg = <0x53100100 0x4>,
568 <0x53100110 0x4>,
569 <0x53100114 0x4>;
578 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
582 ranges = <0x0 0x53100000 0x1000>;
584 sham: sham@0 {
586 reg = <0 0x200>;
588 dmas = <&edma 36 0>;
595 reg = <0x53500080 0x4>,
596 <0x53500084 0x4>,
597 <0x53500088 0x4>;
607 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
611 ranges = <0x0 0x53500000 0x1000>;
613 aes: aes@0 {
615 reg = <0 0xa0>;
617 dmas = <&edma 6 0>,
618 <&edma 5 0>;
625 reg = <0x5600fe00 0x4>,
626 <0x5600fe10 0x4>;
634 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
637 resets = <&prm_gfx 0>;
641 ranges = <0 0x56000000 0x1000000>;
643 gpu@0 {
645 reg = <0x0 0x10000>; /* 64kB */
658 reg = <0xc00 0x100>;
660 #power-domain-cells = <0>;
665 reg = <0xd00 0x100>;
667 #power-domain-cells = <0>;
672 reg = <0xe00 0x100>;
673 #power-domain-cells = <0>;
678 reg = <0xf00 0x100>;
684 reg = <0x1000 0x100>;
685 #power-domain-cells = <0>;
690 reg = <0x1100 0x100>;
691 #power-domain-cells = <0>;
697 reg = <0x1200 0x100>;
698 #power-domain-cells = <0>;
704 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
705 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
709 timer@0 {
717 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
718 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
722 timer@0 {