Lines Matching +full:fixed +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
22 clock-mult = <1>;
23 clock-div = <1>;
26 dcan0_fck: clock-dcan0-fck {
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
29 clock-output-names = "dcan0_fck";
31 clock-mult = <1>;
32 clock-div = <1>;
35 dcan1_fck: clock-dcan1-fck {
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
38 clock-output-names = "dcan1_fck";
40 clock-mult = <1>;
41 clock-div = <1>;
44 mcasp0_fck: clock-mcasp0-fck {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
47 clock-output-names = "mcasp0_fck";
49 clock-mult = <1>;
50 clock-div = <1>;
53 mcasp1_fck: clock-mcasp1-fck {
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
56 clock-output-names = "mcasp1_fck";
58 clock-mult = <1>;
59 clock-div = <1>;
62 smartreflex0_fck: clock-smartreflex0-fck {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-output-names = "smartreflex0_fck";
67 clock-mult = <1>;
68 clock-div = <1>;
71 smartreflex1_fck: clock-smartreflex1-fck {
72 #clock-cells = <0>;
73 compatible = "fixed-factor-clock";
74 clock-output-names = "smartreflex1_fck";
76 clock-mult = <1>;
77 clock-div = <1>;
80 sha0_fck: clock-sha0-fck {
81 #clock-cells = <0>;
82 compatible = "fixed-factor-clock";
83 clock-output-names = "sha0_fck";
85 clock-mult = <1>;
86 clock-div = <1>;
89 aes0_fck: clock-aes0-fck {
90 #clock-cells = <0>;
91 compatible = "fixed-factor-clock";
92 clock-output-names = "aes0_fck";
94 clock-mult = <1>;
95 clock-div = <1>;
98 rng_fck: clock-rng-fck {
99 #clock-cells = <0>;
100 compatible = "fixed-factor-clock";
101 clock-output-names = "rng_fck";
103 clock-mult = <1>;
104 clock-div = <1>;
107 clock@664 {
110 #clock-cells = <2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
114 ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clock-output-names = "ehrpwm0_tbclk";
122 ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clock-output-names = "ehrpwm1_tbclk";
130 ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clock-output-names = "ehrpwm2_tbclk";
140 clk_32768_ck: clock-clk-32768 {
141 #clock-cells = <0>;
142 compatible = "fixed-clock";
143 clock-output-names = "clk_32768_ck";
144 clock-frequency = <32768>;
147 clk_rc32k_ck: clock-clk-rc32k {
148 #clock-cells = <0>;
149 compatible = "fixed-clock";
150 clock-output-names = "clk_rc32k_ck";
151 clock-frequency = <32000>;
154 virt_19200000_ck: clock-virt-19200000 {
155 #clock-cells = <0>;
156 compatible = "fixed-clock";
157 clock-output-names = "virt_19200000_ck";
158 clock-frequency = <19200000>;
161 virt_24000000_ck: clock-virt-24000000 {
162 #clock-cells = <0>;
163 compatible = "fixed-clock";
164 clock-output-names = "virt_24000000_ck";
165 clock-frequency = <24000000>;
168 virt_25000000_ck: clock-virt-25000000 {
169 #clock-cells = <0>;
170 compatible = "fixed-clock";
171 clock-output-names = "virt_25000000_ck";
172 clock-frequency = <25000000>;
175 virt_26000000_ck: clock-virt-26000000 {
176 #clock-cells = <0>;
177 compatible = "fixed-clock";
178 clock-output-names = "virt_26000000_ck";
179 clock-frequency = <26000000>;
182 tclkin_ck: clock-tclkin {
183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-output-names = "tclkin_ck";
186 clock-frequency = <12000000>;
189 dpll_core_ck: clock@490 {
190 #clock-cells = <0>;
191 compatible = "ti,am3-dpll-core-clock";
192 clock-output-names = "dpll_core_ck";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
198 #clock-cells = <0>;
199 compatible = "ti,am3-dpll-x2-clock";
200 clock-output-names = "dpll_core_x2_ck";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
205 #clock-cells = <0>;
206 compatible = "ti,divider-clock";
207 clock-output-names = "dpll_core_m4_ck";
209 ti,max-div = <31>;
211 ti,index-starts-at-one;
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
215 #clock-cells = <0>;
216 compatible = "ti,divider-clock";
217 clock-output-names = "dpll_core_m5_ck";
219 ti,max-div = <31>;
221 ti,index-starts-at-one;
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
225 #clock-cells = <0>;
226 compatible = "ti,divider-clock";
227 clock-output-names = "dpll_core_m6_ck";
229 ti,max-div = <31>;
231 ti,index-starts-at-one;
234 dpll_mpu_ck: clock@488 {
235 #clock-cells = <0>;
236 compatible = "ti,am3-dpll-clock";
237 clock-output-names = "dpll_mpu_ck";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
243 #clock-cells = <0>;
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_mpu_m2_ck";
247 ti,max-div = <31>;
249 ti,index-starts-at-one;
252 dpll_ddr_ck: clock@494 {
253 #clock-cells = <0>;
254 compatible = "ti,am3-dpll-no-gate-clock";
255 clock-output-names = "dpll_ddr_ck";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
261 #clock-cells = <0>;
262 compatible = "ti,divider-clock";
263 clock-output-names = "dpll_ddr_m2_ck";
265 ti,max-div = <31>;
267 ti,index-starts-at-one;
270 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clock-output-names = "dpll_ddr_m2_div2_ck";
275 clock-mult = <1>;
276 clock-div = <2>;
279 dpll_disp_ck: clock@498 {
280 #clock-cells = <0>;
281 compatible = "ti,am3-dpll-no-gate-clock";
282 clock-output-names = "dpll_disp_ck";
287 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
288 #clock-cells = <0>;
289 compatible = "ti,divider-clock";
290 clock-output-names = "dpll_disp_m2_ck";
292 ti,max-div = <31>;
294 ti,index-starts-at-one;
295 ti,set-rate-parent;
298 dpll_per_ck: clock@48c {
299 #clock-cells = <0>;
300 compatible = "ti,am3-dpll-no-gate-j-type-clock";
301 clock-output-names = "dpll_per_ck";
306 dpll_per_m2_ck: clock-dpll-per-m2@4ac {
307 #clock-cells = <0>;
308 compatible = "ti,divider-clock";
309 clock-output-names = "dpll_per_m2_ck";
311 ti,max-div = <31>;
313 ti,index-starts-at-one;
316 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
317 #clock-cells = <0>;
318 compatible = "fixed-factor-clock";
319 clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
321 clock-mult = <1>;
322 clock-div = <4>;
325 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
326 #clock-cells = <0>;
327 compatible = "fixed-factor-clock";
328 clock-output-names = "dpll_per_m2_div4_ck";
330 clock-mult = <1>;
331 clock-div = <4>;
334 clk_24mhz: clock-clk-24mhz {
335 #clock-cells = <0>;
336 compatible = "fixed-factor-clock";
337 clock-output-names = "clk_24mhz";
339 clock-mult = <1>;
340 clock-div = <8>;
343 clkdiv32k_ck: clock-clkdiv32k {
344 #clock-cells = <0>;
345 compatible = "fixed-factor-clock";
346 clock-output-names = "clkdiv32k_ck";
348 clock-mult = <1>;
349 clock-div = <732>;
352 l3_gclk: clock-l3-gclk {
353 #clock-cells = <0>;
354 compatible = "fixed-factor-clock";
355 clock-output-names = "l3_gclk";
357 clock-mult = <1>;
358 clock-div = <1>;
361 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
362 #clock-cells = <0>;
363 compatible = "ti,mux-clock";
364 clock-output-names = "pruss_ocp_gclk";
369 mmu_fck: clock-mmu-fck-1@914 {
370 #clock-cells = <0>;
371 compatible = "ti,gate-clock";
372 clock-output-names = "mmu_fck";
374 ti,bit-shift = <1>;
378 timer1_fck: clock-timer1-fck@528 {
379 #clock-cells = <0>;
380 compatible = "ti,mux-clock";
381 clock-output-names = "timer1_fck";
386 timer2_fck: clock-timer2-fck@508 {
387 #clock-cells = <0>;
388 compatible = "ti,mux-clock";
389 clock-output-names = "timer2_fck";
394 timer3_fck: clock-timer3-fck@50c {
395 #clock-cells = <0>;
396 compatible = "ti,mux-clock";
397 clock-output-names = "timer3_fck";
402 timer4_fck: clock-timer4-fck@510 {
403 #clock-cells = <0>;
404 compatible = "ti,mux-clock";
405 clock-output-names = "timer4_fck";
410 timer5_fck: clock-timer5-fck@518 {
411 #clock-cells = <0>;
412 compatible = "ti,mux-clock";
413 clock-output-names = "timer5_fck";
418 timer6_fck: clock-timer6-fck@51c {
419 #clock-cells = <0>;
420 compatible = "ti,mux-clock";
421 clock-output-names = "timer6_fck";
426 timer7_fck: clock-timer7-fck@504 {
427 #clock-cells = <0>;
428 compatible = "ti,mux-clock";
429 clock-output-names = "timer7_fck";
434 usbotg_fck: clock-usbotg-fck-8@47c {
435 #clock-cells = <0>;
436 compatible = "ti,gate-clock";
437 clock-output-names = "usbotg_fck";
439 ti,bit-shift = <8>;
443 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
444 #clock-cells = <0>;
445 compatible = "fixed-factor-clock";
446 clock-output-names = "dpll_core_m4_div2_ck";
448 clock-mult = <1>;
449 clock-div = <2>;
452 ieee5000_fck: clock-ieee5000-fck-1@e4 {
453 #clock-cells = <0>;
454 compatible = "ti,gate-clock";
455 clock-output-names = "ieee5000_fck";
457 ti,bit-shift = <1>;
461 wdt1_fck: clock-wdt1-fck@538 {
462 #clock-cells = <0>;
463 compatible = "ti,mux-clock";
464 clock-output-names = "wdt1_fck";
469 l4_rtc_gclk: clock-l4-rtc-gclk {
470 #clock-cells = <0>;
471 compatible = "fixed-factor-clock";
472 clock-output-names = "l4_rtc_gclk";
474 clock-mult = <1>;
475 clock-div = <2>;
478 l4hs_gclk: clock-l4hs-gclk {
479 #clock-cells = <0>;
480 compatible = "fixed-factor-clock";
481 clock-output-names = "l4hs_gclk";
483 clock-mult = <1>;
484 clock-div = <1>;
487 l3s_gclk: clock-l3s-gclk {
488 #clock-cells = <0>;
489 compatible = "fixed-factor-clock";
490 clock-output-names = "l3s_gclk";
492 clock-mult = <1>;
493 clock-div = <1>;
496 l4fw_gclk: clock-l4fw-gclk {
497 #clock-cells = <0>;
498 compatible = "fixed-factor-clock";
499 clock-output-names = "l4fw_gclk";
501 clock-mult = <1>;
502 clock-div = <1>;
505 l4ls_gclk: clock-l4ls-gclk {
506 #clock-cells = <0>;
507 compatible = "fixed-factor-clock";
508 clock-output-names = "l4ls_gclk";
510 clock-mult = <1>;
511 clock-div = <1>;
514 sysclk_div_ck: clock-sysclk-div {
515 #clock-cells = <0>;
516 compatible = "fixed-factor-clock";
517 clock-output-names = "sysclk_div_ck";
519 clock-mult = <1>;
520 clock-div = <1>;
523 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
524 #clock-cells = <0>;
525 compatible = "fixed-factor-clock";
526 clock-output-names = "cpsw_125mhz_gclk";
528 clock-mult = <1>;
529 clock-div = <2>;
532 cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
533 #clock-cells = <0>;
534 compatible = "ti,mux-clock";
535 clock-output-names = "cpsw_cpts_rft_clk";
540 gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
541 #clock-cells = <0>;
542 compatible = "ti,mux-clock";
543 clock-output-names = "gpio0_dbclk_mux_ck";
548 lcd_gclk: clock-lcd-gclk@534 {
549 #clock-cells = <0>;
550 compatible = "ti,mux-clock";
551 clock-output-names = "lcd_gclk";
554 ti,set-rate-parent;
557 mmc_clk: clock-mmc {
558 #clock-cells = <0>;
559 compatible = "fixed-factor-clock";
560 clock-output-names = "mmc_clk";
562 clock-mult = <1>;
563 clock-div = <2>;
566 clock@52c {
569 #clock-cells = <2>;
570 #address-cells = <1>;
571 #size-cells = <0>;
573 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
575 #clock-cells = <0>;
576 compatible = "ti,mux-clock";
577 clock-output-names = "gfx_fclk_clksel_ck";
581 gfx_fck_div_ck: clock-gfx-fck-div@0 {
583 #clock-cells = <0>;
584 compatible = "ti,divider-clock";
585 clock-output-names = "gfx_fck_div_ck";
587 ti,max-div = <2>;
591 clock@700 {
594 #clock-cells = <2>;
595 #address-cells = <1>;
596 #size-cells = <0>;
598 sysclkout_pre_ck: clock-sysclkout-pre@0 {
600 #clock-cells = <0>;
601 compatible = "ti,mux-clock";
602 clock-output-names = "sysclkout_pre_ck";
606 clkout2_div_ck: clock-clkout2-div@3 {
608 #clock-cells = <0>;
609 compatible = "ti,divider-clock";
610 clock-output-names = "clkout2_div_ck";
612 ti,max-div = <8>;
615 clkout2_ck: clock-clkout2@7 {
617 #clock-cells = <0>;
618 compatible = "ti,gate-clock";
619 clock-output-names = "clkout2_ck";
626 per_cm: clock@0 {
627 compatible = "ti,omap4-cm";
628 clock-output-names = "per_cm";
630 #address-cells = <1>;
631 #size-cells = <1>;
634 l4ls_clkctrl: clock@38 {
636 clock-output-names = "l4ls_clkctrl";
638 #clock-cells = <2>;
641 l3s_clkctrl: clock@1c {
643 clock-output-names = "l3s_clkctrl";
645 #clock-cells = <2>;
648 l3_clkctrl: clock@24 {
650 clock-output-names = "l3_clkctrl";
652 #clock-cells = <2>;
655 l4hs_clkctrl: clock@120 {
657 clock-output-names = "l4hs_clkctrl";
659 #clock-cells = <2>;
662 pruss_ocp_clkctrl: clock@e8 {
664 clock-output-names = "pruss_ocp_clkctrl";
666 #clock-cells = <2>;
669 cpsw_125mhz_clkctrl: clock@0 {
671 clock-output-names = "cpsw_125mhz_clkctrl";
673 #clock-cells = <2>;
676 lcdc_clkctrl: clock@18 {
678 clock-output-names = "lcdc_clkctrl";
680 #clock-cells = <2>;
683 clk_24mhz_clkctrl: clock@14c {
685 clock-output-names = "clk_24mhz_clkctrl";
687 #clock-cells = <2>;
691 wkup_cm: clock@400 {
692 compatible = "ti,omap4-cm";
693 clock-output-names = "wkup_cm";
695 #address-cells = <1>;
696 #size-cells = <1>;
699 l4_wkup_clkctrl: clock@0 {
701 clock-output-names = "l4_wkup_clkctrl";
703 #clock-cells = <2>;
706 l3_aon_clkctrl: clock@14 {
708 clock-output-names = "l3_aon_clkctrl";
710 #clock-cells = <2>;
713 l4_wkup_aon_clkctrl: clock@b0 {
715 clock-output-names = "l4_wkup_aon_clkctrl";
717 #clock-cells = <2>;
721 mpu_cm: clock@600 {
722 compatible = "ti,omap4-cm";
723 clock-output-names = "mpu_cm";
725 #address-cells = <1>;
726 #size-cells = <1>;
729 mpu_clkctrl: clock@0 {
731 clock-output-names = "mpu_clkctrl";
733 #clock-cells = <2>;
737 l4_rtc_cm: clock@800 {
738 compatible = "ti,omap4-cm";
739 clock-output-names = "l4_rtc_cm";
741 #address-cells = <1>;
742 #size-cells = <1>;
745 l4_rtc_clkctrl: clock@0 {
747 clock-output-names = "l4_rtc_clkctrl";
749 #clock-cells = <2>;
753 gfx_l3_cm: clock@900 {
754 compatible = "ti,omap4-cm";
755 clock-output-names = "gfx_l3_cm";
757 #address-cells = <1>;
758 #size-cells = <1>;
761 gfx_l3_clkctrl: clock@0 {
763 clock-output-names = "gfx_l3_clkctrl";
765 #clock-cells = <2>;
769 l4_cefuse_cm: clock@a00 {
770 compatible = "ti,omap4-cm";
771 clock-output-names = "l4_cefuse_cm";
773 #address-cells = <1>;
774 #size-cells = <1>;
777 l4_cefuse_clkctrl: clock@0 {
779 clock-output-names = "l4_cefuse_clkctrl";
781 #clock-cells = <2>;