Lines Matching +full:0 +full:x2690000
27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
34 reg = <0x0 0x02561000 0x0 0x1000>,
35 <0x0 0x02562000 0x0 0x2000>,
36 <0x0 0x02564000 0x0 0x2000>,
37 <0x0 0x02566000 0x0 0x2000>;
66 cpu_suspend = <0x84000001>;
67 cpu_off = <0x84000002>;
68 cpu_on = <0x84000003>;
71 soc0: soc@0 {
76 ranges = <0x0 0x0 0x0 0xc0000000>;
77 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
81 reg = <0x02310000 0x200>;
86 reg = <0x02350000 0x1000>;
91 reg = <0x02620000 0x1000>;
94 ranges = <0x0 0x02620000 0x1000>;
98 reg = <0x2a0 0x4>;
102 ti,syscon-dev = <&devctrl 0x2a0>;
107 reg = <0x328 0x10>;
108 ti,syscon-pll = <&pllctrl 0xe4>;
109 ti,syscon-dev = <&devctrl 0x328>;
110 ti,wdt-list = <0>;
121 reg = <0x02530c00 0x100>;
131 reg = <0x02531000 0x100>;
138 reg = <0x02530000 0x400>;
143 #size-cells = <0>;
148 reg = <0x02530400 0x400>;
153 #size-cells = <0>;
158 reg = <0x02530800 0x400>;
163 #size-cells = <0>;
168 reg = <0x21000400 0x200>;
170 ti,davinci-spi-intr-line = <0>;
174 #size-cells = <0>;
179 reg = <0x21000600 0x200>;
181 ti,davinci-spi-intr-line = <0>;
185 #size-cells = <0>;
190 reg = <0x21000800 0x200>;
192 ti,davinci-spi-intr-line = <0>;
196 #size-cells = <0>;
203 reg = <0x2620738 24>;
211 reg = <0x2680000 0x10000>;
222 reg = <0x2690000 0x70000>;
230 reg = <0x022f0080 0x80>;
236 reg = <0x022f0000 0x80>;
243 reg = <0x0260bf00 0x100>;
293 reg = <0x21000a00 0x00000100>;
294 ranges = <0 0 0x30000000 0x10000000
295 1 0 0x21000a00 0x00000100>;
304 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
305 ranges = <0x82000000 0 0x50000000 0x50000000
306 0 0x10000000>;
311 bus-range = <0x00 0xff>;
316 interrupt-map-mask = <0 0 0 7>;
317 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
318 <0 0 0 2 &pcie_intc0 1>, /* INT B */
319 <0 0 0 3 &pcie_intc0 2>, /* INT C */
320 <0 0 0 4 &pcie_intc0 3>; /* INT D */
349 reg = <0x21010000 0x200>;