Lines Matching +full:0 +full:xc3000000
24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x00 0x00101010 0x00f0f0f0
207 0x04 0x00000110 0x00000ff0
213 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
214 0x1c 0x10110010 0xf0ff00f0
216 * EMA_D[0], EMA_D[1], EMA_D[2],
220 0x24 0x11111111 0xffffffff
226 0x20 0x11111111 0xffffffff
228 0x30 0x01100000 0x0ff00000
235 pinctrl-0 = <&serial2_rxtx_pins>;
262 pinctrl-0 = <&mdio_pins>;
269 pinctrl-0 = <&mii_pins>;
277 pinctrl-0 = <&mmc0_pins>;
284 pinctrl-0 = <&i2c0_pins>;
289 #sound-dai-cells = <0>;
291 reg = <0x18>;
305 #sound-dai-cells = <0>;
307 pinctrl-0 = <&mcasp0_pins>;
310 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
312 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
313 0 0 0 0
314 0 0 0 0
315 0 0 0 0
316 0 1 2 0
336 pinctrl-0 = <&nand_pins>;
346 nand@2000000,0 {
350 reg = <0 0x02000000 0x02000000
351 1 0x00000000 0x00008000>;
354 ti,davinci-mask-ale = <0>;
355 ti,davinci-mask-cle = <0>;
356 ti,davinci-mask-chipsel = <0>;
366 * to NAND block 1 (NAND block 0 is not used by default)".
368 * "Updated NAND boot mode to offer boot from block 0 or block 1".
378 partition@0 {
380 reg = <0 0x020000>;
385 reg = <0x020000 0x080000>;
389 reg = <0x0a0000 0>;
407 pinctrl-0 = <&lcd_pins>;
418 pinctrl-0 = <&vpif_capture_pins>;