Lines Matching +full:0 +full:x10040000
31 reg = <0xC0000000 0x10000000>;
41 reg = <0x10000000 0x40000>;
47 reg = <0x10040000 0x1000>;
53 reg = <0x10041000 0x1000>;
59 reg = <0x10042000 0x4000>;
65 reg = <0x30000000 0x40000>;
71 reg = <0x38000000 0x10000>;
94 pinctrl-0 = <&adc12_pins_mecsbc>;
105 channel@0 {
106 reg = <0>;
204 pinctrl-0 = <ðernet0_rgmii_pins_x>;
214 #size-cells = <0>;
232 pinctrl-0 = <&pinctrl_hog_d_mecsbc>;
291 pinctrl-0 = <&i2c2_pins_a>;
297 reg = <0x20>;
308 reg = <0x21>;
320 pinctrl-0 = <&qspi_clk_pins_a
328 flash@0 {
330 reg = <0>;
354 pinctrl-0 = <&pwm1_pins_mecio1>;
367 pinctrl-0 = <&pwm8_pins_mecio1>;
375 pinctrl-0 = <&uart4_pins_a>;
395 pinctrl-0 = <&usbotg_hs_pins_a>;
397 phys = <&usbphyc_port1 0>;
416 adc12_pins_mecsbc: adc12-ain-mecsbc-0 {
422 <STM32_PINMUX('A', 0, ANALOG)>, /* ADC1_INP16 */
427 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
429 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
434 pinctrl_hog_d_mecsbc: hog-d-0 {
439 slew-rate = <0>;
443 pwm1_pins_mecio1: pwm1-mecio1-0 {
449 slew-rate = <0>;
453 pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 {
460 pwm8_pins_mecio1: pwm8-mecio1-0 {
466 slew-rate = <0>;
470 pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 {
477 ethernet0_rgmii_pins_x: rgmii-0 {
495 slew-rate = <0>;
508 ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {